The device contains a Device Manager
(DM) to handle all of the low-level power management control of the device including
the Low Power Mode transitions. It is part of the DM Always ON (AON) power domain as
shown in Figure 6-5.
A firmware is provided by Texas Instruments that includes all of the necessary
functions to achieve low power modes. Inter-Processor Communication (IPC) registers
are available to communicate with the Device Manager so the user can provide certain
configuration parameters based on the level of low power that is required.
The followings are prerequisites to start a low power mode sequence.
- All IO Pad config MMRs configured appropriately for a target low power
mode
- Save device configuration / context information to external DDR
- Power initiator, likely A53
running RTOS or Linux or MCU M4 running
RTOS, is responsible for putting other application cores in proper state
(OFF) and restarts after resume.
- Power initiator core will signal for DM sleep sequence to begin.
- Application software is responsible for DS padconf configuration for all
states needed in low power mode.
- Secure Stub must be signed and encrypted as a bootable image and loaded to
SPS region by HLOS or bootloader
- DM Stub must be loaded to
NSPS region by HLOS or bootloader
- TISCI_MSG_PREPARE_SLEEP comes from PM initiator (Secure or Non-secure)
- Contains Desired State to Enter (DeepSleep, MCU-Only, Standby)
- Flags that can be used to set HALT points for debug
- Memory address to be used for TIFS context encrypt and save. If bad
address is given on resume, decrypt will fail.
- TISCI_MSG_ENTER_SLEEP message must contain resume address of cores to be
restarted by firmware
- WKUP_CTRL.PMCTRL_SYS.lpm_en should be configured to let DeepSleep Logic
control PMIC_LPM_EN output before sequence.
Sleep Sequencing
- During Active power mode, the MPU sends TISCI_MSG_PREPARE_SLEEP with
DeepSleep selected to the DM and TISCI_MSG_ENTER_SLEEP with resume address
to the TIFS core.
- TIFS Core prepares for DeepSleep and messages HSM core to tell it to enter
WFI
- HSM Core prepares for DeepSleep and enters WFI
- TIFS Core sends TISCI to DM for suspend finish and enters WFI.
- DM waits for all cores to enter WFI, timeout and abort if they do not.
- DM executes DM Stub sequence, place DDR into Self Refresh, configures
selected wakeup sources and HFOSC clock and PD.
- DM enters in WFI
- DS HW Logic gates off HFOSC0 and Powers-off
- DS state is captured in MMR.
- Device in DS state
Wakeup Sequencing
- Event of IO daisy chain or internal Timer/RTC events generates async wake-up
event
- This async wake-up event turns on high frequency oscillator (HFOSC)
- DM exists WFI as soon as HFOSC clock is available.
- DM detects that it is resuming from Deep sleep mode
- DM goes through wake-up sequence: enabling MCU PLL etc
- DM Powers-on MCU, SMS, DEBUGSS
- DM configures
DS_MAIN_POR_PDOFF register to deassert MCU PORz and Main PD Domains (SMS,
DEBUGSS, MAINIP)
- Wait for RESETSTATz
indication to determine Main is out of Reset
- TIFS Boots-up -it detects
that it is resuming from DeepSleep state
- DM and TIFS handshake to start the device restore
- Decrypts Secure Stub from DM Secure RAM and Messages DM on completion
- DM configures Main Domain PLLs
- DM programs Main PSC to enable clocks to Main components (DDR, USB,
Peripherals)
- DM checks PSC to ensure DDR and USB are enabled and resets are
de-asserted.
- DM configures DDR to restore to the state it was prior to entering sleep
mode
- DM enables A53 –enables PLLs, programs Reset Vector, etc...
- A53 reads context data from external DDR and restores MAIN/WKUP/MCU
configuration including IO pads etc
- Device enters normal mode of operation
Note: Low Power Mode sequencing is
controlled via Device Manager. For more information how to use Device Manager, see
TISCI API available at ti.com.