SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
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| Instance Name | Physical Address |
|---|---|
| DDR16SS0 | 0F30 C170h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_RDDATA_EN_DLY_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WDQLVL_IE_ON_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DBI_MODE_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:29 | RESERVED | NONE | 0h | Reserved |
| 28:24 | PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0 | R/W | 0h | For WR DQ training, the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 0. Reset Source: ctl_amod_g_rst_n |
| 23:21 | RESERVED | NONE | 0h | Reserved |
| 20:16 | PHY_WDQLVL_RDDATA_EN_DLY_0 | R/W | 0h | For WR DQ training, the number of cycles that the dfi_rddata_en signal is early for slice 0. Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | PHY_WDQLVL_IE_ON_0 | R/W | 0h | IE control, 1 meams IE is always on during WR DQ training for slice 0. Reset Source: ctl_amod_g_rst_n |
| 7:2 | RESERVED | NONE | 0h | Reserved |
| 1:0 | PHY_DBI_MODE_0 | R/W | 0h | DBI mode for slice 0. Bit [0] enables return of DBI read data. Reset Source: ctl_amod_g_rst_n |