SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
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| Instance Name | Physical Address |
|---|---|
| WKUP_CTRL_MMR0 | 4301 4004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHNG_DDR4_FSP_ACK_ACK | RESERVED | CHNG_DDR4_FSP_ACK_ERROR | |||||
| R | NONE | R | |||||
| X | 0h | X | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | NONE | 0h | Reserved |
| 7 | CHNG_DDR4_FSP_ACK_ACK | R | X | Frequency change acknowledge. This bit is only valid when CHNG_DDR4_FSP_REQ_req = 1 Indication from the DDR Controller that the FSP change operation is complete 0 - FSP change operation in progress 1 - FSP change operation complete Reset Source: mod_por_rst_n |
| 6:1 | RESERVED | NONE | 0h | Reserved |
| 0 | CHNG_DDR4_FSP_ACK_ERROR | R | X | Frequency change error This bit is only valid when CHNG_DDR4_FSP_REQ_req = 1 0 - FSP change was sucessful 1 - FSP change was not sucessful Reset Source: mod_por_rst_n |