SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Performance Monitors Common Event Identification Register 1
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| Instance Name | Physical Address |
|---|---|
| A53SS0 | 0007 3032 0E24h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RES0_PMCEID1_EL0_31_1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RES0_PMCEID1_EL0_31_1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RES0_PMCEID1_EL0_31_1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0_PMCEID1_EL0_31_1 | CE_32 | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:1 | RES0_PMCEID1_EL0_31_1 | R/W | 0h | Reserved, RES0. |
| 0 | CE_32 | R/W | 0h | Common architectural and microarchitectural feature events that can be counted by the PMU event counters.For the bit described in the following table, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0.BitEvent numberEvent mnemonic00x020L2D_CACHE_ALLOCATE |