| RTI0 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=0 |
functional clock |
| RTI0 |
FCLK |
HFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=0 |
functional clock |
| RTI0 |
FCLK |
CLK_32K |
MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| RTI0 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| RTI0 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| RTI0 |
FCLK |
LFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| RTI0 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=2 |
functional clock |
| RTI0 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL[1:0]=3 |
functional clock |
| RTI0 |
ICLK |
MAIN_SYSCLK0/4 |
|
interface clock |
| RTI1 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=0 |
functional clock |
| RTI1 |
FCLK |
HFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=0 |
functional clock |
| RTI1 |
FCLK |
CLK_32K |
MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| RTI1 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| RTI1 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| RTI1 |
FCLK |
LFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| RTI1 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=2 |
functional clock |
| RTI1 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL[1:0]=3 |
functional clock |
| RTI1 |
ICLK |
MAIN_SYSCLK0/4 |
|
interface clock |
| RTI2 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=0 |
functional clock |
| RTI2 |
FCLK |
HFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=0 |
functional clock |
| RTI2 |
FCLK |
CLK_32K |
MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| RTI2 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| RTI2 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| RTI2 |
FCLK |
LFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| RTI2 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=2 |
functional clock |
| RTI2 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_WWD2_CLKSEL[1:0]=3 |
functional clock |
| RTI2 |
ICLK |
MAIN_SYSCLK0/4 |
|
interface clock |
| RTI3 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=0 |
functional clock |
| RTI3 |
FCLK |
HFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=0 |
functional clock |
| RTI3 |
FCLK |
CLK_32K |
MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| RTI3 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| RTI3 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| RTI3 |
FCLK |
LFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| RTI3 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=2 |
functional clock |
| RTI3 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_WWD3_CLKSEL[1:0]=3 |
functional clock |
| RTI3 |
ICLK |
MAIN_SYSCLK0/4 |
|
interface clock |
| RTI15 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=0 |
functional clock |
| RTI15 |
FCLK |
HFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=0 |
functional clock |
| RTI15 |
FCLK |
CLK_32K |
MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| RTI15 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| RTI15 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| RTI15 |
FCLK |
LFOSC0 (INSTANCE) |
MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| RTI15 |
FCLK |
CLK_12M_RC |
MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=2 |
functional clock |
| RTI15 |
FCLK |
CLK_32K_RC |
MAIN_CTRL_MMR_CFG0_WWD15_CLKSEL[1:0]=3 |
functional clock |
| RTI15 |
ICLK |
MAIN_SYSCLK0/4 |
|
interface clock |
| MCU_RTI0 |
FCLK |
CLK_12M_RC |
MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=0 |
functional clock |
| MCU_RTI0 |
FCLK |
HFOSC0 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=0 |
functional clock |
| MCU_RTI0 |
FCLK |
CLK_32K |
MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| MCU_RTI0 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| MCU_RTI0 |
FCLK |
CLK_32K_RC |
MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| MCU_RTI0 |
FCLK |
LFOSC0 (INSTANCE) |
MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| MCU_RTI0 |
FCLK |
CLK_12M_RC |
MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=2 |
functional clock |
| MCU_RTI0 |
FCLK |
CLK_32K_RC |
MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL[1:0]=3 |
functional clock |
| MCU_RTI0 |
ICLK |
MCU_SYSCLK0/4 |
|
interface clock |
| WKUP_RTI0 |
FCLK |
CLK_12M_RC |
WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=0 |
functional clock |
| WKUP_RTI0 |
FCLK |
HFOSC0 (INSTANCE) |
WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=0 |
functional clock |
| WKUP_RTI0 |
FCLK |
CLK_32K |
WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0 |
functional clock |
| WKUP_RTI0 |
FCLK |
MCU_HSDIV0_16FFT32 (INSTANCE) |
WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1 |
functional clock |
| WKUP_RTI0 |
FCLK |
CLK_32K_RC |
WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2 |
functional clock |
| WKUP_RTI0 |
FCLK |
LFOSC0 (INSTANCE) |
WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=1
MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3 |
functional clock |
| WKUP_RTI0 |
FCLK |
CLK_12M_RC |
WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=2 |
functional clock |
| WKUP_RTI0 |
FCLK |
CLK_32K_RC |
WKUP_CTRL_MMR_CFG0_WKUP_WWD0_CLKSEL[1:0]=3 |
functional clock |
| WKUP_RTI0 |
ICLK |
DM_CLK/4 |
|
interface clock |