SPRUIV7 User guide | 德州仪器 TI.com.cn

SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP

14.2.1.2.1 Pad Configuration Register Functional Description

The pad configuration registers are used to configure most of the device pads. Each pad configuration register is associated only with one pad and has bits as described in Table 14-5487.

Table 14-5487 Description Of The Pad Configuration Register Bits

Bit	Field	Type	Reset	Description
31	LOCK	R/W	⁽¹⁾	Pad configuration register lock bit. 0h - The corresponding pad configuration register is unlocked. Its value can be modified. Further writes are allowed. 1h - The corresponding pad configuration register is locked. Its value can not be modified. Further writes are not allowed. Once the padconfig is locked a reset is the only allowed option to modify the padconfig. The lock bit can be reset only by PORz (MCU and Main Domain cold reset) event.
30	WKUP_EVT	R/W	⁽¹⁾	Wakeup event status 0h - No wake event on pin 1h - Wake event occurred on pin
29	WKUP_EN	R/W	⁽¹⁾	Wakeup enable 0h - Wakeup operation disabled 1h - Wakeup operation enabled
28	DS_PULLTYPE_SEL	R/W	⁽¹⁾	Deep Sleep pull-up/down selection 0h - Offmode pulldown selected 1h - Offmode pullup selected
27	DS_PULLUD_EN	R/W	⁽¹⁾	Deep Sleep pull-up/down enable (active low) 0h - Pullup / pulldown is enabled 1h - Pullup / pulldown is disabled
26	DSOUT_VAL	R/W	⁽¹⁾	Deep Sleep output value 0h - Output value is 0 1h - Output value is 1
25	DSOUT_DIS	R/W	⁽¹⁾	Deep Sleep output disable 0h - Output enabled 1h - Output disabled
24	DS_EN	R/W	⁽¹⁾	Deep Sleep override control 0h - IO keeps its previous state when Deep Sleep mode is active 1h - IO state is forced to OFF mode value when Deep Sleep mode is active
23	ISO_BYP	R/W	⁽¹⁾	Isolation Bypass 0h - IO isolation is preserved 1h - IO isolation is bypassed During Deepsleep mode and IO+DDR mode, we can configure IOs to generate a wake-up event to exit the low power mode. In this mode IOs go into low power retention state (driver is disabled and receiver is ON) and are hooked up in a daisy chain. If you do not want a particular IO to enter this mode, you can program ISO_BYP to bypass this mode.
22	RESERVED	R/W		Reserved
21	TX_DIS⁽³⁾	R/W	⁽¹⁾	Driver Disable 0h - Driver is enabled 1h - Driver is disabled
20 - 19	DRV_STR⁽⁴⁾	R/W	⁽¹⁾	Drive Strength Control. Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types) 0h - Nominal 1h - Reserved 2h - Fast 3h - Reserved Note: The nominal (default) DRV_STR settings should be used to ensure timings, unless specific instructions are given otherwise.
18	RXACTIVE⁽⁵⁾	R/W	⁽¹⁾	Input enable for the Pad 0h - Receiver disabled 1h - Receiver enabled
17	PULLTYPESEL⁽²⁾	R/W	⁽¹⁾	Pad Pullup / Pulldown type selection 0h - Pulldown selected 1h - Pullup selected
16	PULLUDEN⁽²⁾	R/W	⁽¹⁾	Pad Pullup / Pulldown enable. This is an active low signal. 0h - Pullup / Pulldown enabled 1h - Pullup / Pulldown disabled
15	FORCE_DS_EN	R/W	⁽¹⁾	Enable pad Deep Sleep controls by overriding DMSC gating 0h - Deep Sleep pad controls are gated by the DMSC 1h - Activate Deep Sleep pad controls (override DMSC gating logic)
14	ST_EN	R/W	⁽¹⁾	Receiver Schmitt Trigger enable 0h - Schmitt trigger input disabled 1h - Schmitt trigger input enabled
13 - 11	DEBOUNCE_SEL	R/W	⁽¹⁾	Selects the debounce period for select input signals. See I/O Debounce Control Registers for more information. 0h - Deactivated 1h - Selects debounce value defined by MCU_CTRL_MMR_CFG0_DBOUNCE_CFG1 2h - Selects debounce value defined by MCU_CTRL_MMR_CFG0_DBOUNCE_CFG2 3h - Selects debounce value defined by MCU_CTRL_MMR_CFG0_DBOUNCE_CFG3 4h - Selects debounce value defined by MCU_CTRL_MMR_CFG0_DBOUNCE_CFG4 5h - Selects debounce value defined by MCU_CTRL_MMR_CFG0_DBOUNCE_CFG5 6h - Selects debounce value defined by MCU_CTRL_MMR_CFG0_DBOUNCE_CFG6 7h - Reserved
10 - 9	RESERVED	R/W	0	Reserved
8	WK_LVL_POL	R/W	⁽¹⁾	Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1h. 0h - Low. A low (0) value on the pin causes a wakeup 1h - High. A high (1) value on the pin causes a wakeup
7	WK_LVL_EN	R/W	⁽¹⁾	Level Sensitive Wakeup Enable 0h - Disabled. Wakeup is triggered by change of the pin input value 1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)
6 - 4	RESERVED	R/W	0	Reserved
3 - 0	MUXMODE	R/W	⁽¹⁾	Pad functional signal mux selection Field values (others are reserved): 0h - Mux Mode 0 1h - Mux Mode 1 2h - Mux Mode 2 3h - Mux Mode 3 4h - Mux Mode 4 5h - Mux Mode 5 6h - Mux Mode 6 7h - Mux Mode 7 8h - Mux Mode 8 9h - Mux Mode 9 Ah - Mux Mode 10 Bh - Mux Mode 11 Ch - Mux Mode 12 Dh - Mux Mode 13 Eh - Mux Mode 14 Fh - Mux Mode 15

(1) See Pad Configuration Registers for reset values for Pad Configuration registers.

(2) These bits do not apply to "I2C OD FS" buffer types as these IOs do not have internal pull registers.

(3) To prevent unwanted glitches, software should disable the output driver by setting the TX_DIS bit before writing a new MUXMODE value. Once the new MUXMODE value is written, the TX_DIS bit can be reset in order to re-enable the pin driver.

(4) Use of settings other than the reset value could invalidate datasheet timings.

(5) The RXACTIVE bit must never be set without a valid logic state being sourced to the pin associated with the respective PADCONFIG register. This is very important since a floating input may damage the device.

Many of the device pads support pad multiplexing. This means that their function can be independently chosen from two or more options. The selection of functions available on each pad is enumerated in table “Pin Multiplexing” of the device-specific Datasheet. The desired function is selected via the MUXMODE field of the associated pad configuration register.