SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
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| Instance Name | Physical Address |
|---|---|
| MCU_CTRL_MMR0 | 0451 A170h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | RST_CTRL_DM_WDT_RST_EN_Z_PROXY | RESERVED | RST_CTRL_MCU_RESET_ISO_DONE_Z_PROXY | RST_CTRL_MCU_ESM_ERROR_RST_EN_Z_PROXY | RST_CTRL_SMS_COLD_RESET_EN_Z_PROXY | ||
| NONE | R/W | NONE | R/W | R/W | R/W | ||
| 0h | 1h | 0h | 0h | 1h | 0h | ||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RST_CTRL_SW_MCU_WARMRST_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | Fh | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RST_CTRL_SW_MAIN_POR_PROXY | RST_CTRL_SW_MAIN_WARMRST_PROXY | ||||||
| R/W | R/W | ||||||
| Fh | Fh | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:23 | RESERVED | NONE | 0h | Reserved |
| 22 | RST_CTRL_DM_WDT_RST_EN_Z_PROXY | R/W | 1h | Deactivate Reset from DM WDT propogating to MCU domain: 0 - Activated 1 - Deactivated Reset Source: mcu_chip1_rst_n |
| 21:19 | RESERVED | NONE | 0h | Reserved |
| 18 | RST_CTRL_MCU_RESET_ISO_DONE_Z_PROXY | R/W | 0h | MCU can set this bit to block warm reset in the main domain which is useful when the MCU may be accessing main domain resources (peripherals, memory..). In this case, the MCU will be notified via an interrupt that there is an outstanding warm reset request for the main domain. Once notified, MCU needs to finish any outstanding operations in has with main domain resources and then clear this bit. After this bit is cleared, the main domain warm reset will unblocked and the warm reset sequence may continue. 0 - Reset of Main Domain is not Blocked by MCU Domain 1 - Reset of Main Domain is Blocked by MCU Domain Reset Source: mcu_chip1_rst_n |
| 17 | RST_CTRL_MCU_ESM_ERROR_RST_EN_Z_PROXY | R/W | 1h | Deactivate Reset of MCU by ESM 0 - Activated 1 - Deactivated Reset Source: mcu_chip1_rst_n |
| 16 | RST_CTRL_SMS_COLD_RESET_EN_Z_PROXY | R/W | 0h | Deactivate Reset of MCU by SMS 0 - Activated 1 - Deactivated Reset Source: mcu_chip1_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11:8 | RST_CTRL_SW_MCU_WARMRST_PROXY | R/W | Fh | This is a fault tolerant bitfield. Causes MCU Domain Warm Reset when set to 4'b0110, Bits will reset to 4'b1111 Reset Source: mcu_chip1_rst_n |
| 7:4 | RST_CTRL_SW_MAIN_POR_PROXY | R/W | Fh | This is a fault tolerant bitfield. Causes MAIN Domain Power On Reset when set to 4'b0110, Bits will reset to 4'b1111 Reset Source: main_chip1_rst_n |
| 3:0 | RST_CTRL_SW_MAIN_WARMRST_PROXY | R/W | Fh | This is a fault tolerant bitfield. Causes MAIN Domain Warm Reset when set to 4'b0110, Bits will reset to 4'b1111 Reset Source: main_chip1_rst_n |