SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
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| Instance Name | Physical Address |
|---|---|
| CTRL_MMR0 | 0010 A2E4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| AUDIO_REFCLK1_CTRL_CLKOUT_EN_PROXY | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | AUDIO_REFCLK1_CTRL_CLK_SEL_PROXY | ||||||
| NONE | R/W | ||||||
| 0h | 7h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15 | AUDIO_REFCLK1_CTRL_CLKOUT_EN_PROXY | R/W | 0h | AUDIO_REFCLK 1 output activate This bit is inverted to drive the active low output buffer activate 0 - AUDIO_EXT_REFCLK1 pin is configured as an input 1 - AUDIO_EXT_REFCLK1 pin is configured as an output Reset Source: mod_g_rst_n |
| 14:3 | RESERVED | NONE | 0h | Reserved |
| 2:0 | AUDIO_REFCLK1_CTRL_CLK_SEL_PROXY | R/W | 7h | Selects the source of AUDIO_REFCLK1 Field values (others are reserved): 3'b000 - MCASP0_AHCLKR 3'b001 - MCASP1_AHCLKR 3'b010 - MCASP2_AHCLKR 3'b011 - MCASP0_AHCLKX 3'b100 - MCASP1_AHCLKX 3'b101 - MCASP2_AHCLKX 3'b110 - MAIN_PLL1_HSDIV6_CLKOUT 3'b111 - MAIN_PLL2_HSDIV8_CLKOUT Reset Source: mod_g_rst_n |