SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
| Instance | MAIN | MCU | WKUP |
|---|---|---|---|
| DSS0 | ✓ |
| Module Instance | Power Sleep Controller | Power Domain | Module Domain | Index | Default | Controllable | Dependencies |
|---|---|---|---|---|---|---|---|
| DSS0 | PSC0 | PD_DSS | LPSC_DSS | 51 | OFF | YES | LPSC_main_IP |
| Module Instance | Module Clock Input | Source Clock | Source Control Register | Description |
|---|---|---|---|---|
| DSS0 | DPI_0_IN_CLK | MAIN_PLL16_HSDIV0_CLKOUT | pixel clock intput to video pipeline | |
| DSS0 | DPI_0_IN_CLK | MAIN_PLL16_HSDIV0_CLKOUT | pixel clock intput to video pipeline | |
| DSS0 | DPI_1_IN_CLK | MAIN_PLL17_HSDIV0_CLKOUT | MAIN_CTRL_MMR_CFG0_DSS_DISPC0_CLKSEL1[0:0]=0 | pixel clock input to video lite pipeline |
| DSS0 | DPI_1_IN_CLK | VOUT0_EXTPCLKIN (PIN) | MAIN_CTRL_MMR_CFG0_DSS_DISPC0_CLKSEL1[0:0]=1 | pixel clock input to video lite pipeline |
| DSS0 | DSS_FUNC_CLK | MAIN_SYSCLK0/2 | dss main functional clock for the controller and peripheral interface ports to system interconnect, and all of the display controller (dispc) logic. |
| Module Instance | Source | Description |
|---|---|---|
| DSS0 | PSC0 | DSS0 reset |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| DSS0 | DSS0_dispc_intr_req_0_0 | MCU_M4FSS0_CORE0_nvic_40 | MCU_M4FSS0_CORE0 | DSS0 interrupt request | level |
| DSS0 | DSS0_dispc_intr_req_0_0 | GICSS0_spi_116 | GICSS0 | DSS0 interrupt request | level |
| DSS0 | DSS0_dispc_intr_req_0_0 | WKUP_R5FSS0_CORE0_intr_24 | WKUP_R5FSS0_CORE0 | DSS0 interrupt request | level |
| DSS0 | DSS0_dispc_intr_req_1_0 | MCU_M4FSS0_CORE0_nvic_41 | MCU_M4FSS0_CORE0 | DSS0 interrupt request | level |
| DSS0 | DSS0_dispc_intr_req_1_0 | GICSS0_spi_117 | GICSS0 | DSS0 interrupt request | level |
| DSS0 | DSS0_dispc_intr_req_1_0 | WKUP_R5FSS0_CORE0_intr_25 | WKUP_R5FSS0_CORE0 | DSS0 interrupt request | level |