SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
An active low asynchronous hardware reset is provided to CSI_RX_IF by device LPSC. It is internally resynchronized to the functional clock domain.
A software reset is triggered by configuring the CSIRX_SOFT_RESET bit-fields for protocol reset and/or module reset.