The below lists the clock management settings applicable at PRUSS subsystem level (first level of local power management).
A transition from an ACTIVE/Normal state to an IDLE state is performed as per the sequence:
- The host processor requests that the PRU firmware goes into IDLE state and waits for acknowledgement.
- The host issues Clock Stop Request for each
module in the PRU_ICSS_CGR register with gateable clocks defined at second power
management level (see Section 7.4.3.2)
- The PRUSS acknowledges IDLE Request and send Clock Stop Acknowledge to the host processor.
- The PSC can de-assert PWR_CLK_EN
- The main clocks can get turned off
A transition from an IDLE state to an ACTIVE/ Normal state is performed as per the sequence:
- Turn on the main external clocks
- The PSC can assert PWR_CLK_EN
- The host will need to de-assert Clock Stop
Request for each module, defined in PRU_ICSS_CGR register,
- The PRUSS firmware
need to de-assert Clock Stop Acknowledge for each module defined in PRU_ICSS_CGR
register and then wait for the Clock Stop Acknowledge de-assert
- The PRUSS firmware will de-assert Clock Stop Acknowledge