SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The register configures the attributes of the video window. Shadow register
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| Instance Name | Physical Address |
|---|---|
| DSS0 | 3020 6020h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| LUMAKEYENABLE | GAMMAINVERSION | RESERVED4 | PREMULTIPLYALPHA | RESERVED5 | SELFREFRESH | ||
| R/W | R/W | R | R/W | R | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ARBITRATION | RESERVED6 | VERTICALTAPS | RESERVED2 | BUFPRELOAD | RESERVED7 | SELFREFRESHAUTO | RESERVED9 |
| R/W | R | R/W | R | R/W | R | R/W | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED9 | RESERVED1 | FLIP | FULLRANGE | NIBBLEMODE | COLORCONVENABLE | RESIZEENABLE | |
| R | R | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESIZEENABLE | FORMAT | ENABLE | |||||
| R/W | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | LUMAKEYENABLE | R/W | 0h | Enable Luma Key transparency matching 0 Luma Key operation is disabled 1 Luma Key operation is enabled |
| 30 | GAMMAINVERSION | R/W | 0h | Inverse Gamma support [using the CLUT table] 0 Gamma inversion is disabled 1 Gamma inversion is enabled |
| 29 | RESERVED4 | R | 0h | Reserved |
| 28 | PREMULTIPLYALPHA | R/W | 0h | The field configures the DISPC VID to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data 0 Non premultiplyalpha data color component 1 Premultiplyalpha data color component |
| 27:25 | RESERVED5 | R | 0h | Reserved |
| 24 | SELFREFRESH | R/W | 0h | Enables the self refresh of the video window, from its own DMA buffer only 0 The video pipeline accesses the
interconnect to fetch data from the system
memory
1 The video pipeline does not need any more
to fetch data from memory. Only the DMA
buffer associated with the video1 is used.
It takes effect after the frame has been
loaded in the DMA buffer |
| 23 | ARBITRATION | R/W | 0h | Determines the priority of the video pipeline. The video pipeline is one of the high priority pipelines. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there are only normal priority pipelines sending requests, the round-robin applies between the normal priority pipelines 0 The video pipeline is one of the normal
priority pipelines
1 The video pipeline is one of the high
priority pipelines |
| 22 | RESERVED6 | R | 0h | Reserved |
| 21 | VERTICALTAPS | R/W | 0h | Video Vertical Resize Tap Number. The vertical poly-phase filter can be configured in 3-tap or 5-tap configuration. According to the number of taps, the maximum input picture width is double while using 3-tap compared to 5-tap 0 3 taps are used for the vertical filtering
logic. The 2 other taps are not used. The
associated bit-fields for the 2 other taps
coefficients do not need to be initialized
1 5 taps are used for the vertical filtering
logic |
| 20 | RESERVED2 | R | 0h | Reserved |
| 19 | BUFPRELOAD | R/W | 0h | Video Preload Value 0 H/W prefetches pixels up to the preload
value defined in the preload register
1 H/W prefetches pixels up to high threshold
value |
| 18 | RESERVED7 | R | 0h | Write 0's for future compatibility. Reads return 0 |
| 17 | SELFREFRESHAUTO | R/W | 0h | Automatic self refresh mode 0 The transition from SELFREFRESH disabled to
enabled is controlled SW
1 The transition from SELFREFRESH disabled to
enabled is controlled only by HW |
| 16:14 | RESERVED9 | R | 0h | Reserved |
| 13 | RESERVED1 | R | 0h | Reserved |
| 12 | FLIP | R/W | 0h | Describes the frame buffer flip operation 0 No Flip 1 Frame Buffer is flipped |
| 11 | FULLRANGE | R/W | 0h | Color Space Conversion full range setting 0 Limited Range Selected 1 Full Range Selected |
| 10 | NIBBLEMODE | R/W | 0h | Video Nibble mode [only for 1-, 2- and 4-bpp] 0 Nibble Mode Disabled 1 Nibble Mode Enabled |
| 9 | COLORCONVENABLE | R/W | 0h | Enable the color space conversion. The HW does not enable/disable the conversion based on the pixel format 0 Color Space Conversion Disabled 1 Color Space Conversion Enabled |
| 8:7 | RESIZEENABLE | R/W | 0h | Video Resize Enable 0 Disable both horizontal and vertical
resizing
1 Enable horizontal resizing
2 Enable vertical resizing
3 Enable both horizontal and vertical
resizing |
| 6:1 | FORMAT | R/W | 0h | Video Format. It defines the pixel format when fetching the video frame buffer 0 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 32 33 34 37 38 39 40 41 42 46 47 48 49 61 62 63 |
| 0 | ENABLE | R/W | 0h | Video pipeline Enable 0 Video Pipe Disabled 1 Video Pipe Enabled |