| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_0 |
GICSS0_spi_32 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_0 |
WKUP_R5FSS0_CORE0_intr_32 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_1 |
GICSS0_spi_33 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_1 |
WKUP_R5FSS0_CORE0_intr_33 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_2 |
GICSS0_spi_34 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_2 |
WKUP_R5FSS0_CORE0_intr_34 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_3 |
GICSS0_spi_35 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_3 |
WKUP_R5FSS0_CORE0_intr_35 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_4 |
GICSS0_spi_36 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_4 |
WKUP_R5FSS0_CORE0_intr_36 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_5 |
GICSS0_spi_37 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_5 |
WKUP_R5FSS0_CORE0_intr_37 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_6 |
GICSS0_spi_38 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_6 |
WKUP_R5FSS0_CORE0_intr_38 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_7 |
GICSS0_spi_39 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_7 |
WKUP_R5FSS0_CORE0_intr_39 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_8 |
GICSS0_spi_40 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_8 |
WKUP_R5FSS0_CORE0_intr_40 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_9 |
GICSS0_spi_41 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_9 |
WKUP_R5FSS0_CORE0_intr_41 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_10 |
GICSS0_spi_42 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_10 |
WKUP_R5FSS0_CORE0_intr_42 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_11 |
GICSS0_spi_43 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_11 |
WKUP_R5FSS0_CORE0_intr_43 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_12 |
GICSS0_spi_44 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_12 |
WKUP_R5FSS0_CORE0_intr_44 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_13 |
GICSS0_spi_45 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_13 |
WKUP_R5FSS0_CORE0_intr_45 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_14 |
GICSS0_spi_46 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_14 |
WKUP_R5FSS0_CORE0_intr_46 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_15 |
GICSS0_spi_47 |
GICSS0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_15 |
WKUP_R5FSS0_CORE0_intr_47 |
WKUP_R5FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_16 |
ICSSM0_pr1_iep0_cap_intr_req_0 |
ICSSM0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_17 |
ICSSM0_pr1_iep0_cap_intr_req_1 |
ICSSM0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_18 |
ICSSM0_pr1_iep0_cap_intr_req_2 |
ICSSM0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_19 |
ICSSM0_pr1_iep0_cap_intr_req_3 |
ICSSM0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_20 |
ICSSM0_pr1_iep0_cap_intr_req_4 |
ICSSM0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_21 |
ICSSM0_pr1_iep0_cap_intr_req_5 |
ICSSM0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_22 |
DMASS0_INTAGGR_0_intaggr_levi_pend_24 |
DMASS0_INTAGGR_0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_23 |
DMASS0_INTAGGR_0_intaggr_levi_pend_25 |
DMASS0_INTAGGR_0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_24 |
DMASS0_INTAGGR_0_intaggr_levi_pend_16 |
DMASS0_INTAGGR_0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_25 |
DMASS0_INTAGGR_0_intaggr_levi_pend_17 |
DMASS0_INTAGGR_0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_26 |
DMASS0_INTAGGR_0_intaggr_levi_pend_18 |
DMASS0_INTAGGR_0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_27 |
DMASS0_INTAGGR_0_intaggr_levi_pend_19 |
DMASS0_INTAGGR_0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_28 |
DMASS0_INTAGGR_0_intaggr_levi_pend_20 |
DMASS0_INTAGGR_0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_29 |
DMASS0_INTAGGR_0_intaggr_levi_pend_21 |
DMASS0_INTAGGR_0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_30 |
DMASS0_INTAGGR_0_intaggr_levi_pend_22 |
DMASS0_INTAGGR_0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_31 |
DMASS0_INTAGGR_0_intaggr_levi_pend_23 |
DMASS0_INTAGGR_0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_32 |
ICSSM0_pr1_slv_intr_18 |
ICSSM0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_33 |
ICSSM0_pr1_slv_intr_25 |
ICSSM0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_34 |
MCU_M4FSS0_CORE0_nvic_15 |
MCU_M4FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |
| MAIN_GPIOMUX_INTROUTER0 |
MAIN_GPIOMUX_INTROUTER0_outp_35 |
MCU_M4FSS0_CORE0_nvic_16 |
MCU_M4FSS0_CORE0 |
MAIN_GPIOMUX_INTROUTER0 interrupt request |
pulse |