SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Device is partition into two PSC control portions, each portion has its own dedicated PSC module: PSC0 and MCU PSC.
Table 6-6 presents Power Domain features for the processor.
| PSC | PD name | PD index | GP / PD | Default Power Domain State | PD State Software Controlled |
|---|---|---|---|---|---|
| MCU PSC | GP_Core_CTL_MCU | 0 | GP (1) | AO(3) | NO |
| PD_MCU_M4F | 1 | PD(2) | ON | YES | |
| PSC0 | GP_Core_CTL | 0 | GP(1) | AO(3) | NO |
| PD_ICSSM | 1 | PD(2) | OFF | YES | |
| PD_CPSW | 2 | PD(2) | ON | YES | |
| PD_A53_cluster_0 | 3 | PD(2) | OFF | YES | |
| PD_A53_0 | 4 | PD(2) | OFF | YES | |
| PD_A53_1 | 5 | PD(2) | OFF | YES | |
| PD_A53_2 | 6 | PD(2) | OFF | YES | |
| PSC0 | PD_A53_3 | 7 | PD(2) | OFF | YES |
| PD_GPU | 8 | PD(2) | OFF | YES | |
| PD_DSS | 9 | PD(2) | OFF | YES |