SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
| Instance | MAIN | MCU | WKUP |
|---|---|---|---|
| CBASS_CENTRAL2 | ✓ |
| Module Instance | Module Clock Input | Source Clock | Source Control Register | Description |
|---|---|---|---|---|
| CBASS_CENTRAL2 | HSM_CLK_1_CLK | MAIN_PLL15_HSDIV0_CLKOUT | None | |
| CBASS_CENTRAL2 | HSM_CLK_2_CLK | MAIN_PLL15_HSDIV0_CLKOUT/2 | None | |
| CBASS_CENTRAL2 | HSM_CLK_4_CLK | MAIN_PLL15_HSDIV0_CLKOUT/4 | None | |
| CBASS_CENTRAL2 | MCU_SYSCLK0_2_CLK | MCU_SYSCLK0/2 | None | |
| CBASS_CENTRAL2 | CLK | MAIN_PLL15_HSDIV0_CLKOUT | None | |
| CBASS_CENTRAL2 | MAIN_SYSCLK0_2_CLK | MAIN_SYSCLK0/2 | None |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| CBASS_CENTRAL2 | CBASS_CENTRAL2_default_err_intr_0 | GICSS0_spi_133 | GICSS0 | CBASS_CENTRAL2 interrupt request | level |
| CBASS_CENTRAL2 | CBASS_CENTRAL2_default_err_intr_0 | WKUP_R5FSS0_CORE0_intr_147 | WKUP_R5FSS0_CORE0 | CBASS_CENTRAL2 interrupt request | level |