SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The following sections describe a high-level description of the different power modes of the device. They are listed in order from highest power consumption, lowest wakeup latency (Standby), to lowest power consumption, highest wakeup latency (Partial IO). If your application requires some sort of power management, you must determine which power mode level described below satisfies your requirements. Each level must be evaluated based on power consumed and latency (the time it takes to wakeup to Active mode). Specific values are detailed in the device-specific data sheet. Note that not all modes are supported by software packages supplied by Texas Instruments.
| Low Power Modes | Wakeup Sources | Application State and Use Case |
|---|---|---|
| Partial IO | CANUART I/O Bank pins | The entire SoC is OFF except I/O pins in CANUART I/O Bank to maintain I/O wakeup capability from CANUART I/O Bank I/O pins. |
| DeepSleep | GP Timers, RTC Timer, UART, I2C, WKUP GPIO, I/O Daisy Chain |
Core domain register information will be lost. On-chip peripheral register (context) information of core domain needs to be saved by application to DDR before entering this mode. DDR is in self-refresh. Boot ROM executes and branches to peripheral context restore for wakeup, followed by system resume. This mode is primarily used for Suspend to RAM for battery lifetime or backup operation. |
| MCU Only |
DeepSleep wakeup events, Interrupt events supported in MCU channel |
The MCU subsystem runs at the MCU PLL clock. The rest of the SoC status is the same as DeepSleep. DDR is in self-refresh. MCU can run applications with MCU domain peripherals while in this low power mode. |
| Standby | Any SoC interrupt event |
On-chip contents are fully preserved. Any SoC interrupt event can cause a wakeup event from this low power mode. A53 and MCU M4F are in WFI or Power Down. DDR memory is in self-refresh. The device can run low-level processing with non-Wakeup/MCU domain peripherals and support wakeup from those peripherals. |
| Low Power Modes | Voltage Domain | Power Domain | Clocks | DDR | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VDD_CORE / VDDR_CORE | VDDS_DDR | 1.8 Analog Rails | 1.8V/3.3V I/O Rails | GP_Core_CTL | PD_ICSSM | PD_CPSW | PD_A53_cluster_0 | PD_A53_x | PD_GPU | PD_DSS | GP_Core_CTL_MCU | PD_MCU_M4F | Main OSC | DPLLs | ||
| Partial IO | OFF | OFF | OFF | Partial On | OFF | OFF | OFF | OFF | OFF | OFF | OFF | OFF | OFF | OFF | OFF | OFF |
| DeepSleep | ON | ON | ON | ON | ON | OFF | OFF | OFF | OFF | OFF | OFF | OFF | OFF | OFF | OFF | Self-Refresh |
| MCU Only | ON | ON | ON | ON | ON | OFF | OFF | OFF | OFF | OFF | OFF | ON | ON | ON | MCU DPLL locked | Self-Refresh |
| Standby | ON | ON | ON | ON | ON | ON | ON | ON | ON | ON | ON | ON | ON | ON | Bypass | Self-Refresh |