SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
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| Instance Name | Physical Address |
|---|---|
| WKUP_CTRL_MMR0 | 4301 8090h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PMCTRL_MOSC_OSC_CG_ON_WFI | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PMCTRL_MOSC_SETUP_TIME | ||||||
| NONE | R/W | ||||||
| 0h | BC00h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PMCTRL_MOSC_SETUP_TIME | |||||||
| R/W | |||||||
| BC00h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PMCTRL_MOSC_SETUP_TIME | |||||||
| R/W | |||||||
| BC00h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | PMCTRL_MOSC_OSC_CG_ON_WFI | R/W | 0h | When set by Device Manager - the soc clock gating logic will gate the device manager clock once Device Manager has entered the WFI state. (Note: this was named osc_cg_dis but name didn't match function) Reset Source: mod_g_rst_n |
| 30:20 | RESERVED | NONE | 0h | Reserved |
| 19:0 | PMCTRL_MOSC_SETUP_TIME | R/W | BC00h | Keep the main oscillator clock gates for the number of HFOSC clock cycles This is the time it takes to stabilize the clock source supplier (i.e. Main Oscillator) Reset Source: mod_g_rst_n |