SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
| Instance | MAIN | MCU | WKUP |
|---|---|---|---|
| EPWM0 | ✓ | ||
| EPWM1 | ✓ | ||
| EPWM2 | ✓ |
| Module Instance | Power Sleep Controller | Power Domain | Module Domain | Index | Default | Controllable | Dependencies |
|---|---|---|---|---|---|---|---|
| EPWM0 | PSC0 | GP_Core_CTL | LPSC_main_IP | 34 | ON | YES | LPSC_DM2main_infra_ISO |
| EPWM1 | PSC0 | GP_Core_CTL | LPSC_main_IP | 34 | ON | YES | LPSC_DM2main_infra_ISO |
| EPWM2 | PSC0 | GP_Core_CTL | LPSC_main_IP | 34 | ON | YES | LPSC_DM2main_infra_ISO |
| Module Instance | Module Clock Input | Source Clock | Source Control Register | Description |
|---|---|---|---|---|
| EPWM0 | FICLK | MAIN_SYSCLK0/2 | functional and interface clock | |
| EPWM1 | FICLK | MAIN_SYSCLK0/2 | functional and interface clock | |
| EPWM2 | FICLK | MAIN_SYSCLK0/2 | functional and interface clock |
| Module Instance | Source | Description |
|---|---|---|
| EPWM0 | PSC0 | EPWM0 reset |
| EPWM1 | PSC0 | EPWM1 reset |
| EPWM2 | PSC0 | EPWM2 reset |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| EPWM0 | EPWM0_epwm_etint_0 | MCU_M4FSS0_CORE0_nvic_36 | MCU_M4FSS0_CORE0 | EPWM0 interrupt request | pulse |
| EPWM0 | EPWM0_epwm_etint_0 | GICSS0_spi_229 | GICSS0 | EPWM0 interrupt request | pulse |
| EPWM0 | EPWM0_epwm_etint_0 | ICSSM0_pr1_slv_intr_11 | ICSSM0 | EPWM0 interrupt request | pulse |
| EPWM0 | EPWM0_epwm_synco_o_0 | TIMESYNC_EVENT_ROUTER0_in_8 | TIMESYNC_EVENT_ROUTER0 | EPWM0 interrupt request | level |
| EPWM0 | EPWM0_epwm_syncout_0 | EPWM1_epwm_syncin_0 | EPWM1 | EPWM0 interrupt request | level |
| EPWM0 | EPWM0_epwm_tripzint_0 | ICSSM0_pr1_slv_intr_24 | ICSSM0 | EPWM0 interrupt request | pulse |
| EPWM0 | EPWM0_epwm_tripzint_0 | GICSS0_spi_230 | GICSS0 | EPWM0 interrupt request | pulse |
| EPWM1 | EPWM1_epwm_etint_0 | MCU_M4FSS0_CORE0_nvic_37 | MCU_M4FSS0_CORE0 | EPWM1 interrupt request | pulse |
| EPWM1 | EPWM1_epwm_etint_0 | GICSS0_spi_231 | GICSS0 | EPWM1 interrupt request | pulse |
| EPWM1 | EPWM1_epwm_etint_0 | ICSSM0_pr1_slv_intr_14 | ICSSM0 | EPWM1 interrupt request | pulse |
| EPWM1 | EPWM1_epwm_syncout_0 | EPWM2_epwm_syncin_0 | EPWM2 | EPWM1 interrupt request | level |
| EPWM1 | EPWM1_epwm_tripzint_0 | ICSSM0_pr1_slv_intr_24 | ICSSM0 | EPWM1 interrupt request | pulse |
| EPWM1 | EPWM1_epwm_tripzint_0 | GICSS0_spi_233 | GICSS0 | EPWM1 interrupt request | pulse |
| EPWM2 | EPWM2_epwm_etint_0 | MCU_M4FSS0_CORE0_nvic_38 | MCU_M4FSS0_CORE0 | EPWM2 interrupt request | pulse |
| EPWM2 | EPWM2_epwm_etint_0 | GICSS0_spi_234 | GICSS0 | EPWM2 interrupt request | pulse |
| EPWM2 | EPWM2_epwm_etint_0 | ICSSM0_pr1_slv_intr_5 | ICSSM0 | EPWM2 interrupt request | pulse |
| EPWM2 | EPWM2_epwm_tripzint_0 | ICSSM0_pr1_slv_intr_24 | ICSSM0 | EPWM2 interrupt request | pulse |
| EPWM2 | EPWM2_epwm_tripzint_0 | GICSS0_spi_235 | GICSS0 | EPWM2 interrupt request | pulse |