SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Integration Instruction ATB Data Register
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| Instance Name | Physical Address |
|---|---|
| A53SS0 | 0007 3033 0EECh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RES0_TRCITIDATAR_31_5 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RES0_TRCITIDATAR_31_5 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RES0_TRCITIDATAR_31_5 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0_TRCITIDATAR_31_5 | ATDATAM_31 | ATDATAM_23 | ATDATAM_15 | ATDATAM_7 | ATDATAM_0 | ||
| R/W | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:5 | RES0_TRCITIDATAR_31_5 | R/W | 0h | Reserved RES0 |
| 4 | ATDATAM_31 | R/W | 0h | Drives the ATDATAM[31] output |
| 3 | ATDATAM_23 | R/W | 0h | Drives the ATDATAM[23] output |
| 2 | ATDATAM_15 | R/W | 0h | Drives the ATDATAM[15] output |
| 1 | ATDATAM_7 | R/W | 0h | Drives the ATDATAM[7] output |
| 0 | ATDATAM_0 | R/W | 0h | Drives the ATDATAM[0] output |