SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
(N=0). Core0 interface is used for interrupts for core 0.
| Signal Name | Dir | Default Val | Description |
|---|---|---|---|
| coreN_ramecc_strb | In | 1'b0 | Strobe to sample the incoming serial data |
| coreN_ramecc_txd | In | 1'b0 | Output serial data |
| coreN_ramecc_rxd | Out | 1'b0 | Input serial data |
| coreN_ramecc_pend[1:0] | Out | 2'd0 | Level Interrupt source |