SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
| Instance | MAIN | MCU | WKUP |
|---|---|---|---|
| CBASS0 | ✓ | ||
| MCU_CBASS0 | ✓ | ||
| WKUP_CBASS0 | ✓ |
| Module Instance | Module Clock Input | Source Clock | Source Control Register | Description |
|---|---|---|---|---|
| CBASS0 | CLK | MAIN_SYSCLK0/2 | None | |
| CBASS0 | MAIN_SYSCLK0_2_CLK | MAIN_SYSCLK0/2 | None | |
| CBASS0 | MAIN_SYSCLK0_4_CLK | MAIN_SYSCLK0/4 | None | |
| MCU_CBASS0 | MCU_SYSCLK0_2_CLK | MCU_SYSCLK0/2 | None | |
| MCU_CBASS0 | MCU_SYSCLK0_4_CLK | MCU_SYSCLK0/4 | None | |
| MCU_CBASS0 | CLK | MCU_SYSCLK0/2 | None | |
| WKUP_CBASS0 | DM_CLK_1_CLK | DM_CLK | None | |
| WKUP_CBASS0 | DM_CLK_2_CLK | DM_CLK/2 | None | |
| WKUP_CBASS0 | DM_CLK_4_CLK | DM_CLK/4 | None | |
| WKUP_CBASS0 | DM_CLK_8_CLK | DM_CLK/8 | None | |
| WKUP_CBASS0 | MCU_SYSCLK0_2_CLK | MCU_SYSCLK0/2 | None | |
| WKUP_CBASS0 | MCU_SYSCLK0_4_CLK | MCU_SYSCLK0/4 | None | |
| WKUP_CBASS0 | CLK | DM_CLK | None | |
| WKUP_CBASS0 | MAIN_SYSCLK0_2_CLK | DM_CLK/2 | None | |
| WKUP_CBASS0 | MAIN_SYSCLK0_4_CLK | DM_CLK/4 | None |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| CBASS0 | CBASS0_default_err_intr_0 | GICSS0_spi_133 | GICSS0 | CBASS0 interrupt request | level |
| CBASS0 | CBASS0_default_err_intr_0 | WKUP_R5FSS0_CORE0_intr_147 | WKUP_R5FSS0_CORE0 | CBASS0 interrupt request | level |
| MCU_CBASS0 | MCU_CBASS0_default_err_intr_0 | GICSS0_spi_133 | GICSS0 | MCU_CBASS0 interrupt request | level |
| MCU_CBASS0 | MCU_CBASS0_default_err_intr_0 | WKUP_R5FSS0_CORE0_intr_147 | WKUP_R5FSS0_CORE0 | MCU_CBASS0 interrupt request | level |
| MCU_CBASS0 | MCU_CBASS0_default_err_intr_0 | MCU_M4FSS0_CORE0_nvic_31 | MCU_M4FSS0_CORE0 | MCU_CBASS0 interrupt request | level |
| MCU_CBASS0 | MCU_CBASS0_default_err_intr_0 | WKUP_R5FSS0_CORE0_intr_148 | WKUP_R5FSS0_CORE0 | MCU_CBASS0 interrupt request | level |
| WKUP_CBASS0 | WKUP_CBASS0_default_err_intr_0 | GICSS0_spi_133 | GICSS0 | WKUP_CBASS0 interrupt request | level |
| WKUP_CBASS0 | WKUP_CBASS0_default_err_intr_0 | WKUP_R5FSS0_CORE0_intr_147 | WKUP_R5FSS0_CORE0 | WKUP_CBASS0 interrupt request | level |