SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The PRUSS supports two levels of clock gating. First level gates all clocks inside the PRUSS when requested by the PSC (Power Sleep Controller). The second level allows user software to enable/disable clocks in the PRUSS clock gating register ICSS_CGR_REG to some internal modules, as follows:
The appropriate configuration registers block controls its local module set inside PRUSS.
PRUSS supports different clock speeds for CORE_CLK and IEP_CLK. For more details, please refer to PRUSS CORE Clock Generation and Module Integration –> PRUSS.