SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The PRUSS includes two PRU RISC cores, PRU0 and PRU1. Each PRU supports basic debug functionality as detailed in Table 13-13.
| Capability | Feature | Notes |
|---|---|---|
| Basic Debug | Processor halt | Support user-requested entry into the suspended state |
| Single step | Execution of a single instruction before entering the suspended state | |
| Software breakpoints | Software breakpoints are supported via opcode replacement | |
| Core register access | Access to processor core registers | |
| System memory access | Access to memory from perspective of CPU |