SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
These registers contain the interval match value for the corresponding timers in the CTSET. TINTVLRn are available based on number of timers instantiated.
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| Instance Name | Physical Address |
|---|---|
| DEBUGSS0 | 0007 3C02 284Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| INTERVAL | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| INTERVAL | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| INTERVAL | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INTERVAL | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | INTERVAL | R/W | 0h | Interval match value for the timers in the CTSET |