SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
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| Instance Name | Physical Address |
|---|---|
| MCU_CTRL_MMR0 | 0451 8190h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| VDD_CORE_GLDTC_CTRL_PWDB | VDD_CORE_GLDTC_CTRL_RSTB | RESERVED | |||||
| R/W | R/W | NONE | |||||
| 0h | 0h | 0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | VDD_CORE_GLDTC_CTRL_LP_FILTER_SEL | ||||||
| NONE | R/W | ||||||
| 0h | X | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | VDD_CORE_GLDTC_CTRL_THRESH_HI_SEL | ||||||
| NONE | R/W | ||||||
| 0h | X | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VDD_CORE_GLDTC_CTRL_THRESH_LO_SEL | ||||||
| NONE | R/W | ||||||
| 0h | X | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | VDD_CORE_GLDTC_CTRL_PWDB | R/W | 0h | Power down - active low. 0 - Deactivate all functions 1 - Activate glitch detectors Reset Source: mcu_chip1_rst_n |
| 30 | VDD_CORE_GLDTC_CTRL_RSTB | R/W | 0h | Reset - active low. To ensure proper operation, rstb must be not be de-asserted for at least 100 ns after power-up (pwdb de-asserted). Additionally, rstb must be toggled low at least 200 ns after any change in threshold or low-pass filter settings to prevent abnormal trigger events. 0 - Reset glitch detector flags 1 - Glitch detection flags are activated Reset Source: mcu_chip1_rst_n |
| 29:19 | RESERVED | NONE | 0h | Reserved |
| 18:16 | VDD_CORE_GLDTC_CTRL_LP_FILTER_SEL | R/W | X | Selects the glitch detect low-pass filter bandwidth Field values (others are reserved): 3'b000 - 150 kHz 3'b001 - 125 kHz 3'b010 - 100 kHz 3'b011 - 80 kHz 3'b100 - 60 kHz 3'b101 - 45 kHz 3'b110 - 30 kHz 3'b111 - 15 kHz Reset Source: mcu_chip1_rst_n |
| 15:14 | RESERVED | NONE | 0h | Reserved |
| 13:8 | VDD_CORE_GLDTC_CTRL_THRESH_HI_SEL | R/W | X | Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 93.5% of VDD 6'b000001 - 94.0% of VDD 6'b000010 - 94.5% of VDD 6'b000011 - 95.0% of VDD 6'b000100 - 95.5% of VDD 6'b000101 - 96.0% of VDD 6'b000110 - 96.5% of VDD 6'b000111 - 97.0% of VDD 6'b001000 - 97.5% of VDD 6'b001001 - 98.0% of VDD 6'b001010 - 98.5% of VDD 6'b001011 - 99.0% of VDD 6'b001100 - 99.5% of VDD 6'b001101 - 100.0% of VDD 6'b001110 - 100.5% of VDD 6'b001111 - 101.0% of VDD 6'b010000 - 101.5% of VDD 6'b010001 - 102.0% of VDD 6'b010010 - 102.5% of VDD 6'b010011 - 103.0% of VDD 6'b010100 - 103.5% of VDD 6'b010101 - 104.0% of VDD 6'b010110 - 104.5% of VDD 6'b010111 - 105.0% of VDD 6'b011000 - 105.5% of VDD 6'b011001 - 106.0% of VDD 6'b011010 - 106.5% of VDD 6'b011011 - 107.0% of VDD 6'b011100 - 107.5% of VDD 6'b011101 - 108.0% of VDD 6'b011110 - 108.5% of VDD 6'b011111 - 109.0% of VDD 6'b100000 - 109.5% of VDD 6'b100001 - 110.0% of VDD 6'b100010 - 111.0% of VDD 6'b100011 - 112.0% of VDD 6'b100100 - 113.0% of VDD 6'b100101 - 114.0% of VDD 6'b100110 - 115.0% of VDD 6'b100111 - 116.0% of VDD 6'b101000 - 117.0% of VDD 6'b101001 - 118.0% of VDD 6'b101010 - 119.0% of VDD 6'b101011 - 120.0% of VDD 6'b101100 - 121.0% of VDD 6'b101101 - 122.0% of VDD 6'b101110 - 123.0% of VDD 6'b101111 - 124.0% of VDD 6'b110000 - 125.0% of VDD 6'b110001 - 126.0% of VDD 6'b110010 - 127.0% of VDD 6'b110011 - 128.0% of VDD 6'b110100 - 129.0% of VDD 6'b110101 - 130.0% of VDD 6'b110110 - 131.0% of VDD 6'b110111 - 132.0% of VDD 6'b111000 - 133.0% of VDD 6'b111001 - 134.0% of VDD 6'b111010 - 135.0% of VDD 6'b111011 - 136.0% of VDD 6'b111100 - 137.0% of VDD 6'b111101 - 138.0% of VDD 6'b111110 - 139.0% of VDD 6'b111111 - 140.0% of VDD Reset Source: mcu_chip1_rst_n |
| 7:6 | RESERVED | NONE | 0h | Reserved |
| 5:0 | VDD_CORE_GLDTC_CTRL_THRESH_LO_SEL | R/W | X | Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved): 6'b000000 - 106.5% of VDD 6'b000001 - 106.0% of VDD 6'b000010 - 105.5% of VDD 6'b000011 - 105.0% of VDD 6'b000100 - 104.5% of VDD 6'b000101 - 104.0% of VDD 6'b000110 - 103.5% of VDD 6'b000111 - 103.0% of VDD 6'b001000 - 102.5% of VDD 6'b001001 - 102.0% of VDD 6'b001010 - 101.5% of VDD 6'b001011 - 101.0% of VDD 6'b001100 - 100.5% of VDD 6'b001101 - 100.0% of VDD 6'b001110 - 99.5% of VDD 6'b001111 - 99.0% of VDD 6'b010000 - 98.5% of VDD 6'b010001 - 98.0% of VDD 6'b010010 - 97.5% of VDD 6'b010011 - 97.0% of VDD 6'b010100 - 96.5% of VDD 6'b010101 - 96.0% of VDD 6'b010110 - 95.5% of VDD 6'b010111 - 95.0% of VDD 6'b011000 - 94.5% of VDD 6'b011001 - 94.0% of VDD 6'b011010 - 93.5% of VDD 6'b011011 - 93.0% of VDD 6'b011100 - 92.5% of VDD 6'b011101 - 92.0% of VDD 6'b011110 - 91.5% of VDD 6'b011111 - 91.0% of VDD 6'b100000 - 90.5% of VDD 6'b100001 - 90.0% of VDD 6'b100010 - 89.0% of VDD 6'b100011 - 88.0% of VDD 6'b100100 - 87.0% of VDD 6'b100101 - 86.0% of VDD 6'b100110 - 85.0% of VDD 6'b100111 - 84.0% of VDD 6'b101000 - 83.0% of VDD 6'b101001 - 82.0% of VDD 6'b101010 - 81.0% of VDD 6'b101011 - 80.0% of VDD 6'b101100 - 79.0% of VDD 6'b101101 - 78.0% of VDD 6'b101110 - 77.0% of VDD 6'b101111 - 76.0% of VDD 6'b110000 - 75.0% of VDD 6'b110001 - 74.0% of VDD 6'b110010 - 73.0% of VDD 6'b110011 - 72.0% of VDD 6'b110100 - 71.0% of VDD 6'b110101 - 70.0% of VDD 6'b110110 - 69.0% of VDD 6'b110111 - 68.0% of VDD 6'b111000 - 67.0% of VDD 6'b111001 - 66.0% of VDD 6'b111010 - 65.0% of VDD 6'b111011 - 64.0% of VDD 6'b111100 - 63.0% of VDD 6'b111101 - 62.0% of VDD 6'b111110 - 61.0% of VDD 6'b111111 - 60.0% of VDD Reset Source: mcu_chip1_rst_n |