SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The r30[20-19] (clk_mode[1:0]) value determines the stop condition for PERIF<m>_CLK. There are 4 options available:
| clk_mode_value | Description |
|---|---|
| 0 | Stop low on last RX frame |
| 1 | Stop high on last RX frame |
| 2 | Run continuously |
| 3 | Stop high on last TX bit |
The last RX frame is configured by PRU_ICSS_PRU0_ED_CHm_CFG0_REG[27-16] PRU0_ED_RX_FRAME_SIZEm, and the last TX bit is configured by PRU_ICSS_PRU0_ED_CHm_CFG0_REG[15-11] PRU0_ED_TX_FRAME_SIZEm (where n = 0 or 1 and m = 0 to 2). Each stop condition is shown in Figure 7-28 through Figure 7-31.
Figure 7-28 PERIF<m>_CLK Stop High on Last RX Frame
Figure 7-29 PERIF<m>_CLK Stop Low on Last RX Frame
Figure 7-30 PERIF<m>_CLK Run Continuously
Figure 7-31 PERIF<m>_CLK Stop High on Last TX Bit