SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Performance Monitors Cycle Counter Filter Register
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| Instance Name | Physical Address |
|---|---|
| A53SS0 | 0007 3032 047Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| P | U | NSK | NSU | NSH | M | RES0_PMCCFILTR_EL0_25_0 | |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RES0_PMCCFILTR_EL0_25_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RES0_PMCCFILTR_EL0_25_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0_PMCCFILTR_EL0_25_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | P | R/W | 0h | EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are: 0 Count cycles in EL1. 1 Do not count cycles in EL1. |
| 30 | U | R/W | 0h | EL0 filtering bit. Controls counting in EL0. If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are: 0 Count cycles in EL0. 1 Do not count cycles in EL0. |
| 29 | NSK | R/W | 0h | Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented, this bit is RES0.If the value of this bit is equal to the value of P, cycles in Non-secure EL1 are counted.Otherwise, cycles in Non-secure EL1 are not counted. |
| 28 | NSU | R/W | 0h | Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented, this bit is RES0.If the value of this bit is equal to the value of U, cycles in Non-secure EL0 are counted.Otherwise, cycles in Non-secure EL0 are not counted. |
| 27 | NSH | R/W | 0h | Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented, this bit is RES0. 0 Do not count cycles in EL2. 1 Count cycles in EL2. |
| 26 | M | R/W | 0h | Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented, this bit is RES0.If the value of this bit is equal to the value of P, cycles in Secure EL3 are counted.Otherwise, cycles in Secure EL3 are not counted. |
| 25:0 | RES0_PMCCFILTR_EL0_25_0 | R/W | 0h | Reserved, RES0. |