SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The register configures the base address of the single video buffer. In case of single plane ARGB or YUV, this is the BA. In case of two plane YUV, this is the BA_Y. In case of two plane RGB565-A8, this is the BA_Alpha. BA__0 & BA__1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only BA__0 is used. Shadow register
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| Instance Name | Physical Address |
|---|---|
| DSS0 | 3020 602Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| BA | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| BA | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| BA | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BA | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | BA | R/W | 0h | Video base address. Base address of the video buffer [Aligned on pixel size boundary except for the following. In case of RGB24 packed format, 4-pixel alignment is required. In case of YUV422, 2-pixel alignment is required. In case of YUV420, byte alignment is required] |