SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
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| Instance Name | Physical Address |
|---|---|
| WKUP_CTRL_MMR0 | 4301 8410h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| SLEEP_STATUS_EXITED_SLEEP | RESERVED | SLEEP_STATUS_MAIN_DS | RESERVED | ||||
| R/W1TC | NONE | R/W1TC | NONE | ||||
| 0h | 0h | 0h | 0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SLEEP_STATUS_MAIN_RESETSTATZ | ||||||
| NONE | R | ||||||
| 0h | X | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RSVD | ||||||
| NONE | |||||||
| 0h | X | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | SLEEP_STATUS_EXITED_SLEEP | R/W1TC | 0h | Set when the HFXOSC clock gate is activated (rising edge capture of OSC_CG_ACK). To be read and cleared by DM after exiting WFI as a status signal distinguishing the case where WFI was entered and the clock was stopped, then exited with a wakeup (this bit will be set) from the case where an interrupt or other event caused the WFI sequence to stop and the HFXOSC was never stopped. Reset Source: sys_por_rst_n |
| 30:29 | RESERVED | NONE | 0h | Reserved |
| 28 | SLEEP_STATUS_MAIN_DS | R/W1TC | 0h | Set when the main domain deep sleep power on reset / power domain off is activated. (rising edge detect of am62_wkup_ctrl_mmr.wkup_0.DS_MAIN_por_pdoff_ft_out_ipcfg). This will be checked by the ROM on TIFS upon exiting from reset to determine if it is a power on reset or exiting deep sleep. Reset Source: sys_por_rst_n |
| 27:9 | RESERVED | NONE | 0h | Reserved |
| 8 | SLEEP_STATUS_MAIN_RESETSTATZ | R | X | Reflects the status of the main domain resetz signal Field values (others are reserved): 1'b0 - Main Domain In Reset 1'b1 - Main Domain Out of Reset Reset Source: mod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |