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SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP

12.9.1.2.1.2 Display Timing Diagrams

Figure 12-473 through Figure 12-476 show examples with timing diagrams of synchronization signals and pixel clocks for active matrix panels. The DISPC video ports directly drive these signals, which are related to the programmable fields listed in Table 12-362. For more information, see also Section 12.9.1.4.1.10.7, DISPC VP Timing Generator and Display Panel Settings.

Table 12-362 DISPC Video Port Register Fields for Active Matrix Display

Name	Register	Description
PPL	DSS_VP1_SIZE_SCREEN[11-0] PPL value + 1	Pixels per line
LPP	DSS_VP1_SIZE_SCREEN[27-16] LPP value + 1	Lines per panel
HBP	DSS_VP1_TIMING_H[31-20] HBP value + 1	Horizontal back porch
HFP	DSS_VP1_TIMING_H[19-8] HFP value + 1	Horizontal front porch
HSW	DSS_VP1_TIMING_H[7-0] HSW value + 1	Horizontal synchronization pulse width
VBP	DSS_VP1_TIMING_V[31-20] VBP value	Vertical back porch
VFP	DSS_VP1_TIMING_V[19-8] VFP value	Vertical front porch
VSW	DSS_VP1_TIMING_V[7-0] VSW value + 1	Vertical synchronization pulse width
ALIGN	DSS_VP1_POL_FREQ[18] ALIGN	Alignment between HSYNC and VSYNC assertion
ONOFF	DSS_VP1_POL_FREQ[17] ONOFF	HSYNC and VSYNC pixel clock control
RF	DSS_VP1_POL_FREQ[16] RF	HSYNC and VSYNC pixel clock edge control
IEO	DSS_VP1_POL_FREQ[15] IEO	Invert output enable
IPC	DSS_VP1_POL_FREQ[14] IPC	Invert PCLK
IHS	DSS_VP1_POL_FREQ[13] IHS	Invert HSYNC
IVS	DSS_VP1_POL_FREQ[12] IVS	Invert VSYNC

Active matrix timing configuration 1:
- DSS_VP1_POL_FREQ[17] ONOFF = 0
- DSS_VP1_POL_FREQ[16] RF = 0
  The HSYNC and VSYNC signals are driven on the opposite edge of PCLK from the pixel data.
- DSS_VP1_POL_FREQ[15] IEO = 0
  The DE signal is active high.
- DSS_VP1_POL_FREQ[14] IPC = 0
  The pixel data are driven on the rising edge of PCLK.
- DSS_VP1_POL_FREQ[13] IHS = 0
  The HSYNC signal is active high.
- DSS_VP1_POL_FREQ[12] IVS = 0
  The VSYNC signal is active high.
- DSS_VP1_POL_FREQ[18] ALIGN = 0
  The VSYNC and HSYNC assertion is not aligned.

Figure 12-473 DISPC Display Timing Diagram of Configuration 1 (Start of Frame)

Figure 12-474 DISPC Display Timing Diagram of Configuration 1 (Between Lines)

Figure 12-475 DISPC Display Timing Diagram of Configuration 1 (Between Frames)

Figure 12-476 DISPC Display Timing Diagram of Configuration 1 (End of Frame)

Active matrix timing configuration 2:
- DSS_VP1_POL_FREQ[17] ONOFF = 1
- DSS_VP1_POL_FREQ[16] RF = 1
  The HSYNC and VSYNC signals are driven on the rising edge of PCLK.
- DSS_VP1_POL_FREQ[15] IEO = 1
  The DE signal is active low.
- DSS_VP1_POL_FREQ[14] IPC = 1
  The pixel data is driven on the falling edge of PCLK.
- DSS_VP1_POL_FREQ[13] IHS = 1
  The HSYNC signal is active low.
- DSS_VP1_POL_FREQ[12] IVS = 1
  The VSYNC signal is active low.
- DSS_VP1_POL_FREQ[18] ALIGN = 0
  The VSYNC and HSYNC assertion is not aligned.

Figure 12-477 DISPC Display Timing Diagram of Configuration 2 (Start of Frame)

Figure 12-478 DISPC Display Timing Diagram of Configuration 2 (Between Lines)

Figure 12-479 DISPC Display Timing Diagram of Configuration 2 (Between Frames)

Figure 12-480 DISPC Display Timing Diagram of Configuration 2 (End of Frame)

Active matrix timing configuration 3:
- DSS_VP1_POL_FREQ[17] ONOFF = 1
- DSS_VP1_POL_FREQ[16] RF = 1
  The HSYNC and VSYNC signals are driven on the rising edge of PCLK.
- DSS_VP1_POL_FREQ[15] IEO = 0
  The DE signal is active high.
- DSS_VP1_POL_FREQ[14] IPC = 0
  The pixel data are driven on the rising edge of PCLK.
- DSS_VP1_POL_FREQ[13] IHS = 0
  The HSYNC signal is active high.
- DSS_VP1_POL_FREQ[12] IVS = 0
  The VSYNC signal is active high.
- DSS_VP1_POL_FREQ[18] ALIGN = 0
  The VSYNC and HSYNC assertion is not aligned.

Figure 12-481 DISPC Display Timing Diagram of Configuration 3 (Start of Frame)

Figure 12-482 DISPC Display Timing Diagram of Configuration 3 (Between Lines)

Figure 12-483 DISPC Display Timing Diagram of Configuration 3 (Between Frames)

Figure 12-484 DISPC Display Timing Diagram of Configuration 3 (End of Frame)