SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
This section describes the pixel data bus for RGB formats and shows timing diagrams of transactions and synchronizations.
For the active matrix display type, one pixel per pixel clock is displayed. The diagrams represent the configuration of assertion of the data on the rising edge of the pixel clock. It is possible to program the interface timing to output the data on the falling edge of the pixel clock.
Figure 12-469 through Figure 12-472 show the interface to 12-, 16-, 18-, and 24-bit RGB active matrix displays. Each vertical line represents one output pixel. The width of the data bus can be configured through DSS_VP1_CONTROL[10-8] DATALINES register bitfield.
Figure 12-469 DISPC
Video Port Pixel Data - 12-bit RGB Active Matrix
Figure 12-470 DISPC
Video Port Pixel Data - 16-bit RGB Active Matrix
Figure 12-471 DISPC
Video Port Pixel Data - 18-bit RGB Active Matrix
Figure 12-472 DISPC
Video Port Pixel Data - 24-bit RGB Active Matrix