SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Performance Monitors Configuration Register
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| Instance Name | Physical Address |
|---|---|
| A53SS0 | 0007 3032 0E00h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RES0_PMCFGR_31_20 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RES0_PMCFGR_31_20 | UEN | WT | NA | EX | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 1h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CCD | CC | SIZE | |||||
| R/W | R/W | R/W | |||||
| 1h | 1h | 3Fh | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| N | |||||||
| R/W | |||||||
| 6h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:20 | RES0_PMCFGR_31_20 | R/W | 0h | Reserved, RES0. |
| 19 | UEN | R/W | 0h | User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface, so this bit is RES0. |
| 18 | WT | R/W | 0h | This feature is not supported, so this bit is RES0. |
| 17 | NA | R/W | 0h | This feature is not supported, so this bit is RES0. |
| 16 | EX | R/W | 1h | Export supported. Value is IMPLEMENTATION DEFINED. 0 PMCR_EL0.X is RES0. 1 PMCR_EL0.X is read/write. |
| 15 | CCD | R/W | 1h | Cycle counter has prescale. This is RES1 if AArch32 is supported at any EL, and RES0 otherwise. 0 PMCR_EL0.D is RES0. 1 PMCR_EL0.D is read/write. |
| 14 | CC | R/W | 1h | Dedicated cycle counter [counter 31] supported. This bit is RES1. |
| 13:8 | SIZE | R/W | 3Fh | Size of counters. This field determines the spacing of counters in the memory-map.In v8-A the counters are at doubleword-aligned addresses, and the largest counter is 64-bits, so this field is 0b111111. |
| 7:0 | N | R/W | 6h | Number of counters implemented in addition to the cycle counter, PMCCNTR_EL0. The maximum number of event counters is 31, so bits[7:5] are always RES0. 00000000 Only PMCCNTR_EL0 implemented. 00000001 PMCCNTR_EL0 plus one event counter implemented. and so on up to 0b00011111, which indicates PMCCNTR_EL0 and 31 event counters implemented. |