SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Performance Monitors Overflow Flag Status Clear Register
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| Instance Name | Physical Address |
|---|---|
| A53SS0 | 0007 3032 0C80h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| C | P_X | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| P_X | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| P_X | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| P_X | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | C | R/W | 0h | PMCCNTR_EL0 overflow bit. Possible values are: 0 When read, means the cycle counter has not overflowed. When written, has no effect. 1 When read, means the cycle counter has overflowed. When written, clears the overflow bit to 0. PMCR_EL0.LC is used to control from which bit of PMCCNTR_EL0 [bit 31 or bit 63] an overflow is detected. |
| 30:0 | P_X | R/W | 0h | Event counter overflow clear bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values of each bit are: 0 When read, means that PMEVCNTR<x> has not overflowed. When written, has no effect. 1 When read, means that PMEVCNTR<x> has overflowed. When written, clears the PMEVCNTR<x> overflow bit to 0. |