SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
ASF Interrupt Raw Status Register. A bit set in this raw register indicates a source of ASF fault in the corresponding feature. Writing to either raw or masked status registers, clear both registers. For test purposes, trigger signal interrupt event by writing to the ASF interrupt status test register.
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| Instance Name | Physical Address |
|---|---|
| CSI_RX_IF0 | 3010 1904h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31_7 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_31_7 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_31_7 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_31_7 | ASF_INTEGRITY_ERR | ASF_PROTOCOL_ERR | ASF_TRANS_TO_ERR | ASF_CSR_ERR | ASF_DAP_ERR | ASF_SRAM_UNCORR_ERR | ASF_SRAM_CORR_ERR |
| R | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:7 | RESERVED_31_7 | R | 0h | Reserved, read as 0, ignored on write. |
| 6 | ASF_INTEGRITY_ERR | R/W1TC | 0h | Integrity error interrupt |
| 5 | ASF_PROTOCOL_ERR | R/W1TC | 0h | Protocol error interrupt |
| 4 | ASF_TRANS_TO_ERR | R/W1TC | 0h | Transaction timeouts error interrupt |
| 3 | ASF_CSR_ERR | R/W1TC | 0h | Configuration and status registers error interrupt |
| 2 | ASF_DAP_ERR | R/W1TC | 0h | Data and address paths parity error interrupt |
| 1 | ASF_SRAM_UNCORR_ERR | R/W1TC | 0h | SRAM uncorrectable error interrupt |
| 0 | ASF_SRAM_CORR_ERR | R/W1TC | 0h | SRAM correctable error interrupt |