SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
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| Instance Name | Physical Address |
|---|---|
| CTRL_MMR0 | 0010 A300h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | DPI0_CLK_CTRL_SYNC_CLK_INVDIS_PROXY | DPI0_CLK_CTRL_DATA_CLK_INVDIS_PROXY | |||||
| NONE | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:10 | RESERVED | NONE | 0h | Reserved |
| 9 | DPI0_CLK_CTRL_SYNC_CLK_INVDIS_PROXY | R/W | 0h | Clock edge select for DPI0 sync outputs Note that this value should be the same as the programmed value of DSS_POL_FREQ[16] RF. Reset Source: mod_por_rst_n 0 HSYNC and VSYNC are driven on the falling
edge of clk
1 HSYNC and VSYNC are driven on the rising
edge of clk |
| 8 | DPI0_CLK_CTRL_DATA_CLK_INVDIS_PROXY | R/W | 0h | Clock edge select for DPI0 data outputs Note that this value should be the same as the programmed value of DSS_POL_FREQ[14] IPC. Reset Source: mod_por_rst_n 0 DATA and DE are driven on the falling edge
of clk
1 DATA and DE are driven on the rising edge
of clk |
| 7:0 | RESERVED | NONE | 0h | Reserved |