SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
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| Instance Name | Physical Address |
|---|---|
| CTRL_MMR0 | 0010 A068h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| MAIN_PLL2_CLKSEL_BYPASS_SW_OVRD_PROXY | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| MAIN_PLL2_CLKSEL_BYP_WARM_RST_PROXY | RESERVED | ||||||
| R/W | NONE | ||||||
| 1h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | MAIN_PLL2_CLKSEL_BYPASS_SW_OVRD_PROXY | R/W | 0h | PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL2 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled. Reset Source: sys_por_rst_n |
| 30:24 | RESERVED | NONE | 0h | Reserved |
| 23 | MAIN_PLL2_CLKSEL_BYP_WARM_RST_PROXY | R/W | 1h | PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL2 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behaviot. Because MAIN PLL2 is warm reset insensitive, bypass mode will only be entered (and exited) in the case of a Thermal reset event. Reset Source: main_chip1_rst_n |
| 22:0 | RESERVED | NONE | 0h | Reserved |