SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Table 5-20 shows configuration pins assignment to functions when boot mode is the eMMC Boot using a UDA boot mode (BOOTMODE[6:3]=1000b). Note that eMMC Boot using alternate eMMC Boot (BOOTMODE[6:3]=1001b) does not have any extra bootmode configuration fields. See Section 5.4.4.1 for more information.
| eMMC Boot Configuration Fields | |||
|---|---|---|---|
| BOOTMODE Pins | Field | Value | Description |
| 9 (13(1)) | Port | 0 | MMCSD Port 0 (8 bit width). This bit must be set to 0 |
| 1 | Reserved | ||
| 7 | FS/Raw | 0 | Filesystem mode |
| 1 | Raw Mode | ||
Table 5-21 summarizes the MMCSD pin configuration done by ROM code for eMMC boot on port0 (MMCSD0). eMMC boot on Port 1 (MMCSD1) is not supported.
| Device Pin | Module Signal | Pull Enable | Pull Direction | Driver Index | Rx En/Dis | Pinmux Sel | Pad Configuration Register |
|---|---|---|---|---|---|---|---|
| MMC0_DAT7 | MMC0_DAT7 | Enable | Up | 0 | Enable | 0 | PADCONFIG126 |
| MMC0_DAT6 | MMC0_DAT6 | Enable | Up | 0 | Enable | 0 | PADCONFIG127 |
| MMC0_DAT5 | MMC0_DAT5 | Enable | Up | 0 | Enable | 0 | PADCONFIG128 |
| MMC0_DAT4 | MMC0_DAT4 | Enable | Up | 0 | Enable | 0 | PADCONFIG129 |
| MMC0_DAT3 | MMC0_DAT3 | Enable | Up | 0 | Enable | 0 | PADCONFIG130 |
| MMC0_DAT2 | MMC0_DAT2 | Enable | Up | 0 | Enable | 0 | PADCONFIG131 |
| MMC0_DAT1 | MMC0_DAT1 | Enable | Up | 0 | Enable | 0 | PADCONFIG132 |
| MMC0_DAT0 | MMC0_DAT0 | Disable | NA | 0 | Enable | 0 | PADCONFIG133 |
| MMC0_CLK | MMC0_CLK | Disable | NA | 0 | Enable | 0 | PADCONFIG134 |
| MMC0_CLKLB | MMC0_CLKLB | Disable | NA | 0 | Enable | 0 | PADCONFIG135 |
| MMC0_CMD | MMC0_CMD | Disable | NA | 0 | Enable | 0 | PADCONFIG136 |
MMC0_CLKLB signal is not pinned out on the device. The pinmux configuration enables the input buffer of the internal loopback clock.