SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
This reset signal is the MAIN domain warm reset request (active LOW) controlled by the RESET_REQz HW pin.
When LOW is detected, reset hardware generates an interrupt to processors (A53SS/R5FSS/M4FSS) so they can complete the reset isolation sequence before reset is propagated.
When MCU domain is configured to operate independently, MCU domain reset isolation sequence is completed before propagating the RESETz to MAIN domain.
MCU IOs are not affected.
When MCU domain is not configured as independent, then this reset will also warm reset MCU domain.
This is a MAIN domain warm reset request. First, the reset isolation sequence is applied and then the reset is propagated.
All modules in MAIN domain are reset except for warm reset isolated modules and MAIN domain CTRLMMR register bits which are reset only on MAIN_PORz.
IOs are not affected.
All processor cores are reset (A53SS, SMS, and R5FSS).
Reason for this reset is captured in the CTRLMMR reset source register WKUP_CTRL_MMR_CFG0_RST_SRC. After reset is de-asserted, device will boot-up. During device boot-up, DM R5F secondary boot loader will read the reset status and MCU ACTIVE MAGIC WORD registers and reconfigure the MCU M4F processor accordingly.
The RESET_REQz reset sequence is described below.
RESET_REQz Sequence shows the timing between the RESET_REQz reset signal and the internal RESETz (MAIN domain warm reset) signal. Refer to the datasheet for timing and pulse width requirements.
RESETSTATz:
The RESETSTATz pin indicates the MAIN domain internal reset status (active LOW). This is a reflection of the reset status after the RESET_REQz reset signal (RESET_REQz HW Pin) is asserted.
When LOW, it indicates that the MAIN domain is in internal reset state.
When HIGH, it indicates that the MAIN domain is out of internal reset state.
RESETSTATz Timing shows the timing between the RESET_REQz reset signal and the RESETSTATz output. Refer to the datasheet for timing and pulse width requirements.
For more details see MAIN_RESETSTATz Status Pin.