SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Each PRU (PRU0 and PRU1) has a dedicated 12KB of Instruction Memory which needs to be initialized by an external to PRUSS Host processor before a PRU core executes any instructions.
The PRUSS PRU0/1_IRAM regions are ONLY accessible from controllers, external to the PRUSS (like Arm) when the PRU0/PRU1 is NOT running. The access is via PRUSStarget port on the device CBASS0 interconnect.
| Start Address | PRU0 | PRU1 |
|---|---|---|
| 0000 0000h | 12KB IRAM | 12KB IRAM |