SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The PRU-ICSS Interrupt Controller lines 0 through 31 are mapped to internal events which are generated by PRUSS integrated modules. Lines 32 to 63 can be external and generated from different peripherals or internally generated by the PRUSS integrated modules. An internal MUX routes the signals to be internal or external, and is controlled by the select bit MII_RT_REG.MII_RT_EVENT_EN. Table 7-62 shows mapping of the different PRUSS internally sourced IRQ events to PRUSS INTC interrupt lines 0 through 63.
| Event Number | Source | |
|---|---|---|
| MII_RT_REG.MII_RT_EVENT_EN =1 mode (default) (Internally Generated) | MII_RT_REG .MII_RT_EVENT_EN =0 mode (Externally Generated) | |
| PRUSS INTC | ||
| 63:56 | pr1_slv_intr[63:56]_intr_pend(external) | pr1_slv_intr[63:56]_intr_pend(external) |
| 55 | pr1_mii1_col & pr1_mii1_txen (external) | pr1_slv_intr[55]_intr_pend(external) |
| 54 | PRU1_RX_EOF | pr1_slv_intr[54]_intr_pend(external) |
| 53 | MDIO_MII_LINK[1] | pr1_slv_intr[53]_intr_pend(external) |
| 52 | PORT1_TX_OVERFLOW | pr1_slv_intr[52]_intr_pend(external) |
| 51 | PORT1_TX_UNDERFLOW | pr1_slv_intr[51]_intr_pend(external) |
| 50 | PRU1_RX_OVERFLOW | pr1_slv_intr[50]_intr_pend(external) |
| 49 | PRU1_RX_NIBBLE_ODD | pr1_slv_intr[49]_intr_pend(external) |
| 48 | PRU1_RX_CRC | pr1_slv_intr[48]_intr_pend(external) |
| 47 | PRU1_RX_SOF | pr1_slv_intr[47]_intr_pend(external) |
| 46 | PRU1_RX_SFD | pr1_slv_intr[46]_intr_pend(external) |
| 45 | PRU1_RX_ERR32 | pr1_slv_intr[45]_intr_pend(external) |
| 44 | PRU1_RX_ERR | pr1_slv_intr[44]_intr_pend(external) |
| 43 | pr0_mii0_col and pr0_mii0_txen (external) |
pr1_slv_intr[43]_intr_pend(external) |
| 42 | PRU0_RX_EOF | pr1_slv_intr[42]_intr_pend(external) |
| 41 | MDIO_MII_LINK[0] | pr1_slv_intr[41]_intr_pend(external) |
| 40 | PORT0_TX_OVERFLOW | pr1_slv_intr[40]_intr_pend(external) |
| 39 | PORT0_TX_UNDERFLOW | pr1_slv_intr[39]_intr_pend(external) |
| 38 | PRU0_RX_OVERFLOW | pr1_slv_intr[38]_intr_pend(external) |
| 37 | PRU0_RX_NIBBLE_ODD | pr1_slv_intr[37]_intr_pend(external) |
| 36 | PRU0_RX_CRC | pr1_slv_intr[36]_intr_pend(external) |
| 35 | PRU0_RX_SOF | pr1_slv_intr[35]_intr_pend(external) |
| 34 | PRU0_RX_SFD | pr1_slv_intr[34]_intr_pend(external) |
| 33 | PRU0_RX_ERR32 | pr1_slv_intr[33]_intr_pend(external) |
| 32 | PRU0_RX_ERR | pr1_slv_intr[32]_intr_pend(external) |
| 31:16 | pr1_pru_mst_intr[15:0]_intr_req | |
| 15 | pr1_ecap_intr_req | |
| 14 | sync0_out_pend | |
| 13 | sync1_out_pend | |
| 12 | pr0_latch0_in (input to PRUSS) | |
| 11 | pr0_latch1_in (input to PRUSS) | |
| 10 | pr0_pdi_wd_exp_pend | |
| 9 | pr0_pd_wd_exp_pend | |
| 8 | pr0_digio_event_req | |
| 7 | pr0_iep_tim_cap_cmp_pend | |
| 6 | pr0_uart0_uint_intr_req | |
| 5 | pr0_uart0_utxevt_intr_req | |
| 4 | pr0_uart0_urxevt_intr_req | |
| 3 | reset_iso_req | |
| 2 | pr0_pru1_r31_status_cnt16 | |
| 1 | pr0_pru0_r31_status_cnt16 | |
| 0 | pr0_ecc_err_intr | |