The PRUSS subsystem includes the following main features:
- Two 32-bit load/store RISC CPU cores — Programmable Real-Time Units (PRU0 and PRU1), each with:
- 20 Enhanced General-Purpose Inputs (EGPI) and 20 Enhanced General-Purpose Outputs (EGPO)
- Asynchronous capture [Serial Capture Unit (SCU)] with 3-channel peripheral interface and Sigma-Delta demodulation support
- The 3-channel peripheral interface supports multiple different encoder protocols such as EnDAT 2.2, HDSL, and Tamagawa.
- 12KB program memory per PRU (PRU0_IRAM and
PRU1_IRAM) with ECC
- MAC (Multiplier with optional Accumulation)
- CRC16/CRC32 hardware accelerator
- RX XFR2VBUS
- Scratchpad Memory (SPAD) with 3 banks of 30 × 32-bit registers:
- 3 banks shared between the PRU0 and PRU1 cores
- 32 KB Shared general purpose memory RAM with ECC (SRAM/DRAM2), shared between PRU0 and PRU1
- Two 8 KB (shared) Data Memories with ECC (DRAM0 and DRAM1)
- 36-bit VBUSM Controller Port:
- Optional address translation for all transactions to External Host
- 16 Software Events generated by 2 PRUs
- One Enhanced Capture Module (ECAP0)
- Interrupt Controller (INTC)
- Up to 32 internal events, generated by modules, internal to the PRUSS
- Up to 32 external events, generated by the system
- Supports up to 10 interrupt channels
- Generation of up to 10 Host interrupts:
- Up to 2 Host interrupts, exported from the PRUSS for signaling the Arm interrupt controllers (pulse and level provided)
- Each system event can be enabled and disabled
- Each host event can be enabled and disabled
- Hardware prioritization of events
- One 32-bit VBUSP target port for memory mapped register and internal memories access
- Flexible power management support
- Integrated 32-bit Interconnect