SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 12-4116 lists the memory-mapped registers for the MCAN Subsystem (MCANSS). All register offset addresses not listed in Table 12-4116 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCAN0_SS | 2070 0000h |
MCAN1_SS | 2071 0000h |
Offset | Acronym | Register Name | MCAN0_SS Physical Address | MCAN1_SS Physical Address |
---|---|---|---|---|
0h | MCANSS_PID | Revision Register | 2070 0000h | 2071 0000h |
4h | MCANSS_CTRL | Control Register | 2070 0004h | 2071 0004h |
8h | MCANSS_STAT | Status Register | 2070 0008h | 2071 0008h |
Ch | MCANSS_ICS | Interrupt Clear Shadow Register | 2070 000Ch | 2071 000Ch |
10h | MCANSS_IRS | Interrupt Raw Status Register | 2070 0010h | 2071 0010h |
14h | MCANSS_IECS | Interrupt Enable Clear Shadow Register | 2070 0014h | 2071 0014h |
18h | MCANSS_IE | Interrupt Enable Register | 2070 0018h | 2071 0018h |
1Ch | MCANSS_IES | Interrupt Enable Status Register | 2070 001Ch | 2071 001Ch |
20h | MCANSS_EOI | End Of Interrupt (EOI) Register | 2070 0020h | 2071 0020h |
24h | MCANSS_EXT_TS_PRESCALER | External Timestamp Prescaler Register | 2070 0024h | 2071 0024h |
28h | MCANSS_EXT_TS_UNSERVICED_INTR_CNTR | External Timestamp Unserviced Interrupt Counter Register | 2070 0028h | 2071 0028h |
MCANSS_PID is shown in Figure 12-2121 and described in Table 12-4118.
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Revision Register
The Revision Register contains the major and minor revisions for the MCANSS.
Instance | Physical Address |
---|---|
MCAN0_SS | 2070 0000h |
MCAN1_SS | 2071 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-8E0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL | MAJOR | CUSTOM | MINOR | ||||||||||||
R-Ah | R-1h | R-0h | R-1h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | Business Unit (2h = Processors) |
27-16 | MODULE_ID | R | 8E0h | Module ID |
15-11 | RTL | R | Ah | RTL Revision |
10-8 | MAJOR | R | 1h | Major Revision |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | MINOR | R | 1h | Minor Revision |
MCANSS_CTRL is shown in Figure 12-2122 and described in Table 12-4120.
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Control Register
The Control Register contains general control bits for the MCANSS.
Instance | Physical Address |
---|---|
MCAN0_SS | 2070 0004h |
MCAN1_SS | 2071 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_TS_CNTR_EN | AUTOWAKEUP | WAKEUPREQEN | DBGSUSP_FREE | RESERVED | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R-0h | ||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R | 0h | Reserved |
6 | EXT_TS_CNTR_EN | R/W | 0h | External Timestamp Counter Enable |
5 | AUTOWAKEUP | R/W | 0h | Automatic Wakeup Enable |
4 | WAKEUPREQEN | R/W | 0h | Wakeup Request Enable |
3 | DBGSUSP_FREE | R/W | 1h | Debug Suspend 0h = Honor debug suspend 1h = Disregard debug suspend |
2-0 | RESERVED | R | 0h | Reserved |
MCANSS_STAT is shown in Figure 12-2123 and described in Table 12-4122.
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Status Register
The Status Register provides general status bits for the MCANSS.
Instance | Physical Address |
---|---|
MCAN0_SS | 2070 0008h |
MCAN1_SS | 2071 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE_FDOE | MEM_INIT_DONE | RESERVED | ||||
R-0h | R- | R-0h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | ENABLE_FDOE | R | -h | Enable FD (Flexible Data-Rate) Configuration Reflects the value of mcanss_enable_fdoe configuration port, -h = mcanss_enable_fdoe. |
1 | MEM_INIT_DONE | R | 0h | Memory Initialization 0h = Memory initialization is in progress 1h = Memory intialization done |
0 | RESERVED | R | 0h | Reserved |
MCANSS_ICS is shown in Figure 12-2124 and described in Table 12-4124.
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Interrupt Clear Shadow Register
Write 1h to clear interrupt bits.
Instance | Physical Address |
---|---|
MCAN0_SS | 2070 000Ch |
MCAN1_SS | 2071 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_TS_CNTR_OVFL | ||||||
R-0h | W-0h | ||||||
LEGEND: R = Read Only; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EXT_TS_CNTR_OVFL | W | 0h | External Timestamp Counter Overflow Interrupt Status Write 1h to clear bits. |
MCANSS_IRS is shown in Figure 12-2125 and described in Table 12-4126.
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Interrupt Raw Status Register
Write 1h to set interrupt bits.
Instance | Physical Address |
---|---|
MCAN0_SS | 2070 0010h |
MCAN1_SS | 2071 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_TS_CNTR_OVFL | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EXT_TS_CNTR_OVFL | R/W1S | 0h | External Timestamp Counter Overflow Interrupt Status Write 1h to set bits. |
MCANSS_IECS is shown in Figure 12-2126 and described in Table 12-4128.
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Interrupt Enable Clear Shadow Register
Write 1h to clear interrupt enable bits.
Instance | Physical Address |
---|---|
MCAN0_SS | 2070 0014h |
MCAN1_SS | 2071 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_TS_CNTR_OVFL | ||||||
R-0h | W1C-0h | ||||||
LEGEND: R = Read Only; W1C = Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EXT_TS_CNTR_OVFL | W1C | 0h | External Timestamp Counter Overflow Interrupt Write 1h to clear bits. |
MCANSS_IE is shown in Figure 12-2127 and described in Table 12-4130.
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Interrupt Enable Register
Write 1h to set interrupt bits.
Instance | Physical Address |
---|---|
MCAN0_SS | 2070 0018h |
MCAN1_SS | 2071 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_TS_CNTR_OVFL | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EXT_TS_CNTR_OVFL | R/W1S | 0h | External Timestamp Counter Overflow Interrupt Write 1h to set bits. |
MCANSS_IES is shown in Figure 12-2128 and described in Table 12-4132.
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Interrupt Enable Status Register
Read enabled interrupts.
Instance | Physical Address |
---|---|
MCAN0_SS | 2070 001Ch |
MCAN1_SS | 2071 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_TS_CNTR_OVFL | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EXT_TS_CNTR_OVFL | R | 0h | External Timestamp Counter Overflow Interrupt |
MCANSS_EOI is shown in Figure 12-2129 and described in Table 12-4134.
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End Of Interrupt (EOI) Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MCAN0_SS | 2070 0020h |
MCAN1_SS | 2071 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI | ||||||||||||||||||||||||||||||
R-0h | W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EOI | W | 0h | End Of Interrupt Write with bit position of the targeted interrupt (example: external timestamp is bit 0). Upon write, level interrupt will clear and if unserviced interrupt counter > 1h will issue another pulse interrupt. 0h = EOI value for external timestamp interrupt 1h = EOI value for mcan[0] interrupt 2h = EOI value for mcan[1] interrupt |
MCANSS_EXT_TS_PRESCALER is shown in Figure 12-2130 and described in Table 12-4136.
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External Timestamp Prescaler Register
Instance | Physical Address |
---|---|
MCAN0_SS | 2070 0024h |
MCAN1_SS | 2071 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRESCALER | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-0 | PRESCALER | R/W | 0h | External Timestamp Prescaler Reload Value External timestamp count rate is host clock rate divided by this value with one exception - a value of 0h has the same effect as 1h. |
MCANSS_EXT_TS_UNSERVICED_INTR_CNTR is shown in Figure 12-2131 and described in Table 12-4138.
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External Timestamp Unserviced Interrupts Counter Register
Instance | Physical Address |
---|---|
MCAN0_SS | 2070 0028h |
MCAN1_SS | 2071 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_TS_INTR_CNTR | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4-0 | EXT_TS_INTR_CNTR | R | 0h | Number of Unserviced Rollover Interrupts If > 1h an EOI write will issue another pulse interrupt. |