SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
A single GPMC module is integrated in the device MAIN domain - GPMC0. Figure 12-1614 shows the GPMC0 integration.
Table 12-3218 through Table 12-3221 summarize the integration of GPMC0 in device MAIN domain.
Module Instance | Power Sleep Controller | Power Domain | Module Domain | Interconnect |
---|---|---|---|---|
GPMC0 | PSC0 | PD0 | LPSC9 | CBASS0 |
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
---|---|---|---|---|
GPMC0 | GPMC0_FCLK | MAIN_PLL0_HSDIV3_CLKOUT | PLL0_HSDIV3 | GPMC0 Functional Clock. For more information about clock multiplexing, see CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL in Section 5.1, Control Module (CTRL_MMR). |
MAIN_PLL2_HSDIV7_CLKOUT | PLL2_HSDIV7 | |||
GPMC0_ICLK | MAIN_SYSCLK0/2 | PLLCTRL0 | GPMC0 Interface Clock |
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
---|---|---|---|---|
GPMC0 | GPMC0_RST | MOD_G_RST | LPSC9 | GPMC0 Asynchronous Reset |
Module Instance | Module Interrupt Input | Source Interrupt Signal | Destination | Description | Type |
---|---|---|---|---|---|
GPMC0 | GPMC0_GPMC_SINTERRUPT_0 | GICSS0_SPI_IN_138 | COMPUTE_CLUSTER0 | GPMC0 Interrupt Request | Level |
PRU_ICSSG0_PR1_SLV_IN_90 | PRU_ICSSG0 | ||||
PRU_ICSSG1_PR1_SLV_IN_90 | PRU_ICSSG1 | ||||
R5FSS0_CORE0_INTR_IN_239 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_239 | R5FSS0_CORE1 | ||||
R5FSS1_CORE0_INTR_IN_239 | R5FSS1_CORE0 | ||||
R5FSS1_CORE1_INTR_IN_239 | R5FSS1_CORE1 |
Module Instance | Module Interrupt Input | Source Interrupt Signal | Destination | Description | Type |
---|---|---|---|---|---|
GPMC0 | GPMC0_GPMC_SDMAREQ_0 | DMASS0_INTAGGR0_LEVI_PEND_29 | DMASS0_INTAGGR0 | DMA Event | Level |
GPMC0 interrupts are further described in Section 12.3.3.4.4, GPMC Interrupt Requests.
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.