SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
There are several schemas of memory protection employed inside of the processors. The tables below describe the schema and arrangement. This describes what bits are protected, how they are protected, the behavior when an error is detected and what bits can be disturbed for ECC testing purposes. This also lists the RAMID associated with each memory to the corresponding ECC Aggregator.
The key for the protection schemes is as follows:
Memory | Protection | RAM Arrangement | CPU (Core ECC Aggr) Rams Ram ID | Notes |
---|---|---|---|---|
L1 I-Cache Data | Parity SED | 41 – Parity for 40:21 | 0-3 | Error detection results in both lines being invalidated then refetched from L2 or memory |
40:21 – Instruction | ||||
20 – Parity for 19:0 | ||||
19:0 – Instruction | ||||
L1 I-Cache Tag | Parity SED | 31 – Parity for 30:0 | 4-5 | Error detection results in both lines being invalidated, then line refetched from L2 or memory |
30:0 – Data | ||||
L1 D-cache Data | ECC SECDED | 38:32 – ECC | 6-13 | Error results in line being cleaned and invalidated from L1 with single bit errors corrected as part of eviction. Line refetched from L2 or memory |
31:0 – Data | ||||
L1 D-Cache Tag | Parity SED | 30 – Parity for 29:0 | 14-17 | Cache sizes makes LSB unnecessary (always 0) so they are removed from the actual RAM. Error results in line cleaned and invalidated from L1. SCU duplicate tags are used to get the correct address. Line refetched from L2 or memory |
29:0 – Tag | ||||
L1 D-cache Dirty | Parity SEDSEC | 11:10 – Way 1/3 Dirty copy 2 and 1. Parity for 4 | 18 | Error results in line cleaned and invalidated from L1 with single bit errors corrected as part of the eviction. Only dirty bit is protected. Other bits are just performance hints |
9:8 – Way 0/2 Dirty copy 2 and 1. Parity for 0 | ||||
7 – Way 1/3 Outer Allocation Hint | ||||
6 – Way 1/3 Age | ||||
5:4 – Way 1/3 Partial MOESI | ||||
3 – Way 0/2 Outer Allocation Hint | ||||
2 – Way 0/2 Age | ||||
1:0 – Way 0/2 Partial MOESI | ||||
TLB | Parity SED | 116 – parity for 113:62 | 19-22 | Error detection results in entry invalidated, new pagewalk to refetch. |
115 – Parity for 61:31 | ||||
114 – Parity for 30:0 | ||||
113:62 – Page Attributes | ||||
61:31 – Entry Identifiers | ||||
30:0 – Address | ||||
SCU L1 Duplicate Tag | ECC SECDED | 37:31 - ECC for 30:0 | 23-26 (accessed by each Core's ecc_aggr) | Cache sizes makes LSB unnecessary (always 0) so they are removed from the actual RAM. Corretable Error – Tag rewritten with correct value, access retried Uncorrectable Error – Tag is invalidated |
30:0 - Duplicate Tag |
Memory | Protection | RAM Arrangement | RAM_ID (L2 Cache RAMs) |
Notes |
---|---|---|---|---|
L2 Tag | ECC SECDED | 37:31 – ECC for 30:0 | 0-15 | Cache sizes makes LSB unnecessary
(always 0) so they are removed from the actual RAM. Corretable Error – Tag rewritten with correct value, access retried. Uncorrectable Error – Tag is invalidated |
30:0 - Tag | ||||
L2 Victim | None | – | – | Performance Hint Only – Error has no functional impact |
L2 Data | ECC SECDED | 71:64 – ECC for 63:0 | 16-23 | Error results in Data corrected
inline, access may stall for 1-2 cycles. After correction, line might be evicted |
63:0 – Data | ||||
Branch Predictor | None | – | – | Performance Hint Only – Error has no functional impact |