Using the prempt receive queue requires more blocks to be allocate to the ports receive FIFO. Write a value of decimal 7 to the CPSW_PN_MAX_BLKS_REG_k[7-0] RX_MAX_BLKS bit field, and a value of decimal 13 to the CPSW_PN_MAX_BLKS_REG_k[15-8] TX_MAX_BLKS register for every port to be enabled for IET.
Write the [23-0]MAC_VERIFY_CNT bit field in the Ethernet port CPSW_PN_IET_VERIFY_REG_k register to set the verify/response timeout count. The default is 10ms for Gigabit mode. For other time values or link speeds the verify count should be updated. If CPSW_PN_IET_CONTROL_REG_k[2] MAC_DISABLEVERIFY bit is to be set (this is forced mode) then this step is unneeded.
The CPSW_PN_IET_CONTROL_REG_k[0] MAC_PENABLE bit can be set as desired. No effect will occur until IET_ENABLE is set. This bit enables premptable packets to be prempted by express traffic but does not preclude packets from being sent to the prempt queue.
If verify/response is desired then CPSW_PN_IET_CONTROL_REG_k[3] MAC_LINKFAIL should be cleared by software to enable verify and response packets. Otherwise, MAC_DISABLEVERIFY bit should be set for forced mode. Verification and response will occur immediately after clearing this bit.
Set the IET_ENABLE bit in the CPSW_CONTROL_REG register to enable IET operations.
After preemption has been verified, the CPSW_PN_IET_CONTROL_REG_k[23-16] MAC_PREMPT field is written to configure the FIFO priorities to be sent to the prempt queue (the other priorities with cleared bits go to the express queue). The hardware switch for each queue from express to prempt happens only when there are no packets queued on the priority.