SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
This device includes two R5FSS sunsystems named R5FSS0 and R5FSS1. The R5FSS subsystem includes two Cortex-R5F corex and embedded debug capability, including:
A summary of the R5FSS0, R5FSS1 debug capabilities is detailed in Table 13-8.
Capability | Feature | Notes |
---|---|---|
Basic Debug | Independent debug configuration | Debug resource configuration is performed over a configuration interface that is isolated from functional traffic |
ROM table | Facilitates discovery of debug resources within debug configuration address space | |
Processor halt | Support user-requested entry into the suspended state | |
Single step | Execution of a single instruction before entering the suspended state | |
Software breakpoints | Software breakpoints are supported via opcode replacement | |
Hardware breakpoints | Eight Debug Breakpoint resources support hardware breakpoints | |
Hardware watchpoints | Eight Debug Watchpoint resources support data address breakpoints | |
Core register access | Access to processor core registers | |
System memory access | Access to memory from perspective of CPU | |
Vector catch | Halting in response to an exception | |
Arm® TrustZone® debug authentication | Provisioning for DBGEN and NIDEN | |
Cross Triggering | Debug state | Support for controlling execution state (run, halt) via triggers and creating triggers upon entry into debug state |
PMU | PMU interrupt trigger | |
ETM | Five ETM external triggers (one ETM Trigger, two external out event triggers, two external in event triggers) | |
PMU | Profile Counters | Three counters can be used to count different events available for gathering statistics on the operation of the processor and memory system |
Cycle Counter | One dedicated counter available for counting CPU clock cycles | |
ETM | Triggering Infrastructure | Comprehensive triggering infrastructure supports use of comparators (address, data value, context ID), counters, sequencer state, an external inputs and outputs to control the enabling of trace. |
Instruction trace | Supports tracing of instruction flow | |
Cycle-accurate tracing | Supports inclusion of a precise cycle count of executed instructions. | |
Branch broadcast tracing | Support for tracing branch address details even in circumstances where that information might be discoverable from object code | |
Data tracing | Support for data address and data value tracing |