SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
There is one ADC module integrated in the device MAIN domain - ADC0. Figure 12-3 shows the integration of ADC0.
Table 12-3 through Table 12-6 summarize the integration of ADC0 in device MAIN domain.
Module Instance | Power Sleep Controller | Power Domain | Module Domain | Interconnect |
---|---|---|---|---|
ADC0 | PSC0 | PD0 | LPSC7 | CBASS0 |
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
---|---|---|---|---|
ADC0 | ADC0_VBUS_CLK | SYSCLK0/2 | PLLCTRL0 | ADC0 interface clock |
ADC0_SYS_CLK | MAIN_PLL2_HSDIV9_CLKOUT | PLL2 | ADC0 system clock | |
ADC0_CLK | HFOSC0_CLKOUT(1) | HFOSC0 | ADC0 clock. Output of multiplexer, see Figure 12-3, ADC Integration. Multiplexer control is provided via CTRLMMR_ADC0_CLKSEL[1-0] CLK_SEL bit field. Default state is HFOSC0_CLKOUT. | |
MAIN_PLL1_HSDIV6_CLKOUT | PLL1 | |||
MAIN_PLL2_HSDIV8_CLKOUT | PLL2 | |||
EXT_REFCLK1 | I/O pin |
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
---|---|---|---|---|
ADC0 | ADC0_RST | MOD_G_RST | LPSC7 | ADC0 reset |
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Type | Description |
---|---|---|---|---|---|
ADC0 | ADC0_GEN_LEVEL_0 | GIC500_SS_IN_128 | COMPUTE_CLUSTER0 | Level | ADC0 interrupt request |
R5FSS0_CORE0_INTR_IN_128 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_128 | R5FSS0_CORE1 | ||||
R5FSS1_CORE0_INTR_IN_128 | R5FSS1_CORE0 | ||||
R5FSS1_CORE1_INTR_IN_128 | R5FSS1_CORE1 | ||||
PRU_ICSSG0_PR1_SLV_INTR_IN_91 | PRU_ICSSG0 | ||||
PRU_ICSSG1_PR1_SLV_INTR_IN_91 | PRU_ICSSG1 | ||||
ADC0_ECC_CORRECTED_ERR_LEVEL_0 | ESM0_LVL_IN_0 | ESM0 | Level | ADC0 ECC corrected error interrupt request | |
ADC0_ECC_UNCORRECTED_ERR_LEVEL_0 | ESM0_LVL_IN_64 | ESM0 | Level | ADC0 ECC uncorrected error interrupt request |
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Type | Description |
---|---|---|---|---|---|
ADC0 | ADC0_FIFO0 | ADC12_0_RX_0 | PDMA_ADC_0 | Pulse | ADC0 receive request line |
ADC0_FIFO1 | ADC12_0_RX_1 | PDMA_ADC_0 | Pulse | ADC0 receive request line |
ADC interrupts are further described in Chapter 9, Interrupts.
ADC DMA events are further described in Section 12.1.1.4.1.6, DMA Requests and Section 11.1, DMA.
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.
For more information on the DMA controllers, see Section 11.1, Data Movement Architecture (DMA).