SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
RAT block is responsible to do a region based address translation. For each region, user can define the starting address and size of the region and remapping the transactions to use a new address range. The starting address and region size need to be aligned. For example, if the region size is 16KB, the starting address for that region needs to be 16KB aligned. And region size should be minimum 4KB or larger to avoid transactions cross the region boundaries. Each RAT block supports multiple programmable regions. And it is important that those regions are not overlapping with each other.
Each RAT block supports multiple programmable regions and it is important that those regions are not overlapping with each other.
Table 6-325 shows the register definition for RAT module.
Address Offset | Register Mnemonic | Register Name |
---|---|---|
0x0 | PID | Revision Register |
0x4 | CONFIG | Config Register |
0x20+(a*0x10), a=0..15 | REGION[a]_CTRL | Region Control Register |
0x20+(a*0x10)+0x4, a=0..15 | REGION[a]_BASE | Region Base Register |
0x20+(a*0x10)+0x8, a=0..15 | REGION[a]_TRANS_L | Region Translated Lower Address |
0x20+(a*0x10)+0xc, a=0..15 | REGION[a]_TRANS_U | Region Translated Upper Address |
0x804 | DESTINATION_ID | Destination ID Register |
0x820 | EXCEPTION_LOGGING_CONTROL | Exception Logging Control Register |
0x824 | EXCEPTION_LOGGING_HEADER0 | Exception Logging Header 0 Register |
0x828 | EXCEPTION_LOGGING_HEADER1 | Exception Logging Header 1 Register |
0x82c | EXCEPTION_LOGGING_DATA0 | Exception Logging Data 0 Register |
0x830 | EXCEPTION_LOGGING_DATA1 | Exception Logging Data 1 Register |
0x834 | EXCEPTION_LOGGING_DATA2 | Exception Logging Data 2 Register |
0x838 | EXCEPTION_LOGGING_DATA3 | Exception Logging Data 3 Register |
0x840 | EXCEPTION_PEND_SET | Exception Logging Interrupt Pending Set Register |
0x844 | EXCEPTION_PEND_CLEAR | Exception Logging Interrupt Pending Clear Register |
0x848 | EXCEPTION_ENABLE_SET | Exception Logging Interrupt Enable Set Register |
0x84c | EXCEPTION_ENABLE_CLEAR | Exception Logging Interrupt Enable Clear Register |
0x850 | EOI_REG | EOI Register |
The PID Register contains the major and minor revisions for the module.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:30 | scheme | r | 0x1 | PID register scheme |
29:28 | bu | r | 0x2 | Business Unit: 10 = Processors |
27:16 | func | r | 0x680 | Module ID |
15:11 | rtl | r | 0x8 | RTL revision. Will vary depending on release. |
10:8 | major | r | 0x1 | Major revision |
7:6 | custom | r | 0x0 | Custom |
5:0 | minor | r | 0x0 | Minor revision |
The CONFIG Register contains the configuration values for the module.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:24 | reserved | r | 0x0 | Reserved |
23:16 | addr_width | r | 0x30 | Number of address bits |
15:8 | addrs | r | 0x1 | Number of addresses |
7:0 | regions | r | 0x10 | Number of regions |
REGION[a]_CTRL defines the Control for Region a.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31 | en | rw | 0x0 | Enable for the Region |
30:6 | reserved | r | 0x0 | Reserved |
5:0 | size | rw | 0x0 | Size of the Region in Address Bits. 0 = 1 byte, 1 = 2B, 2 = 4B, 3 = 8B, etc. up to 32 = 4GB. |
REGION[a]_BASE Register defines the Base Address for Region a. This is the source address for matching to a region.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:0 | base | rw | 0x0 | Base Address for the Region. It must be aligned to the programmed size. |
REGION[a]_TRANS_L Register defines the Translated Lower Address Bits for Region A.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:0 | lower | rw | 0x0 | Translated Lower Address Bits for the Region. It must be aligned to the programmed size. |
REGION[a]_TRANS_U Register defines the Translated Upper Address Bits for Region a.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:16 | reserved | r | 0x0 | Reserved |
15:0 | upper | rw | 0x0 | Translated Upper Address Bits for the Region |
DESTINATION_ID Register defines the destination ID for error messages.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:8 | reserved | r | 0x0 | Reserved |
7:0 | dest_id | rw | 0x0 | The destination ID. |
The EXCEPTION_LOGGING_CONTROL Register controls the exception logging.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:2 | reserved | r | 0x0 | Reserved |
1 | disable_intr | rw | 0x0 | Disables logging interrupt when set. This will not disable logging, so if cleared the current log should also be cleared to guarantee the next log generates the interrupt. |
0 | disable_f | rw | 0x0 | Disables logging when set. This will also disable interrupts. |
The EXCEPTION_LOGGING_HEADER0 Register contains the first word of the header.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:24 | type_f | r | 0x0 | Type. 4 = RAT. |
23:8 | src_id | r | 0x0 | Source ID. |
7:0 | dest_id | r | 0x0 | Destination ID. |
The EXCEPTION_LOGGING_HEADER1 Register contains the second word of the header.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:24 | group | r | 0x0 | Group. |
23:16 | code | r | 0x0 | Code. 1 = Boundary crossing error. |
15:0 | reserved | r | 0x0 | Reserved |
The EXCEPTION_LOGGING_DATA0 Register contains the first word of the data.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:0 | addr_l | r | 0x0 | Address lower 32 bits. |
The EXCEPTION_LOGGING_DATA1 Register contains the second word of the data.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:16 | reserved | r | 0x0 | Reserved |
15:0 | addr_h | r | 0x0 | Address upper 12 bits. |
The EXCEPTION_LOGGING_DATA2 Register contains the third word of the data.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:28 | reserved | r | 0x0 | Reserved |
27:16 | routeid | r | 0x0 | Route ID. |
15:14 | reserved | r | 0x0 | Reserved |
13 | write | r | 0x0 | Write. |
12 | read | r | 0x0 | Read. |
11 | debug | r | 0x0 | Debug. |
10 | cacheable | r | 0x0 | Cacheable. |
9 | priv | r | 0x0 | Priv. |
8 | secure | r | 0x0 | Secure. |
7:0 | priv_id | r | 0x0 | Priv ID. |
The EXCEPTION_LOGGING_DATA3 Register contains the fourth word of the data. Reading this register will clear the error pending bit.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:10 | reserved | r | 0x0 | Reserved |
9:0 | bytecnt | r | 0x0 | Byte count. |
The EXCEPTION_PEND_SET Register allows to set the pend signal.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:1 | reserved | r | 0x0 | Reserved |
0 | pend_set | rw1ts | 0x0 | Write a 1 to set the exception pend signal. |
The EXCEPTION_PEND_CLEAR Register allows to clear the pend signal.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:1 | reserved | r | 0x0 | Reserved |
0 | pend_clr | rw1tc | 0x0 | Write a 1 to clear the exception pend signal. |
The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:1 | reserved | r | 0x0 | Reserved |
0 | enable_set | rw1ts | 0x0 | Write a 1 to set the exception interrupt enable signal. |
The EXCEPTION_ENABLE_CLEAR Registerr allows to clear the interrupt enable signal.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:1 | reserved | r | 0x0 | Reserved |
0 | enable_clr | rw1tc | 0x0 | Write a 1 to clear the exception interrupt enable signal. |
EOI_REG Register defines the EOI Register.
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31:16 | reserved | r | 0x0 | Reserved |
15:0 | eoi_wr | rw | 0x0 | EOI Register |
RAT block is by default disabled, which means RAT block does not do address remapping. The 32b address coming from M4F core is directly sent out to the SoC level. The user can program each RAT remapping region individually. For the transactions does not hit any remapping region, RAT block just simply forwards the transactions to the SoC level with its original address.