SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
After the PRU is intilized, the software should only enable Shift Out Mode configuration per intilization.
Follow these steps to use the GPO shift out mode:
Step 1: Initialization
Continous Mode (Free running clock mode) (ICSSG_GPECFG0_REG[5] PRU0_GPO_SHIFT_CLK_FREE = 1h):
Follow these steps to use the GPO Fixed Packet Length mode:
Fixed Packet Length Mode: (ICSSG_GPECFG0_REG[5] PRU0_GPO_SHIFT_CLK_FREE = 0h):
To enable this mode, the software should prepare the precondition to get the PRU<n>_CLOCKOUT and PRU<n>_DATAOUT in the correct defined state.
Precondition:
After the precondition is executed, PRU<n>_CLOCKOUT and PRU<n>_DATAOUT are in the correct state, then the user can configure ICSSG_GPCFG0_REG[14] PRU0_GPO_MODE = 1h (Serial Mode).
After this operation is completed then the software controls the length of the packet along with the number of clock cycles in addition to the idle state of the clock.
ICSSG_GPECFG0_REG[15-8] PRU0_GPO_SHIFT_CNT bit field defines the number of bits shifted out.
This enables the software to fully control the state of shift data (PRU<n>_DATAOUT) for the first edge event. For stop low (PRU0_GPO_SHIFT_CLK_HIGH = 0h), the first edge event is rising edge, the first bit of new data is shifted 1 full clock cycle before the first rising edge seen on the shift clock (ICSSG<n>_CORE_CLK). For stop high (PRU0_GPO_SHIFT_CLK_HIGH = 1h), the first edge event is falling edge, the first bit of new data is shifted 1/2 full clock cycle before the first falling edge seen on shift clock (ICSSG<n>_CORE_CLK).
Send Data
Active Data Loop:
1. Monitor when a shadow register has finished shifting out data and can be loaded with new data:
(a) Poll PRU0_GPO_SH1_SEL bit in the ICSSG_GPCFG0_REG register (PRU0 or PRU1)
(b) Load new 16-bits of data into GPO_SH0 if PRU0_GPO_SH1_SEL = 1h
(c) Exit loop if PRU0_GPO_SHIFT_CLK_DONE = 1h
2. If more data needs to be send, loop to Active Data Loop:
(a) Poll PRU0_GPO_SH1_SEL bit of the ICSSG_GPCFG0_REG register (PRU0 or PRU1)
(b) Load new 16-bits of data into GPO_SH1 if PRU0_GPO_SH1_SEL = 0h
(c) Jump to Active Data loop if PRU0_GPO_SHIFT_CLK_DONE = 0h
(d) Exit loop if PRU0_GPO_SHIFT_CLK_DONE = 1h
Exit:
1. Write 1h to PRU0_GPO_SHIFT_CLK_DONE bit to clear.
2. Clear R30[31] = 0h (enable shift)
3. If more data packets need to be send go to Send Data
4. If no more data, exit loop
Note: Idle time between packets must be greater than 4 clock cycles.
Until the shift operation is disabled, the shift loop will continue looping and shifting out the pre-loaded data if no new data has been loaded into GPO_SH0/1.