SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
This section describes module integration in the device, including information about clocks, resets, and hardware requests.
This section describes the CPTS in the MAIN domain
For CPTS in PCIe integration, see Section 12.2.2.4.9, PCIe Subsystem Precision Time Measurement (PTM) in Section 12.2.2, Peripheral Component Interconnect Express (PCIe) Subsystem.
For CPTS in CPSW integration, refer to Section 12.2.1.3 in Section 12.2.1, Gigabit Ethernet Switch (CPSW0).
Figure 10-2 shows the CPTS0 integration.
Table 10-2 and Table 10-3 summarize the integration of the module in the device.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
CPTS0 | PSC0 | GP | LPSC0 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
CPTS0 | CPTS0_ICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | CPTS0 interface clock |
CPTS0_RCLK | MAIN_PLL2_HSDIV5_CLKOUT | MAIN_PLL2 | CPTS0 reference clock. Selectable in CTRL_MMR
CTRLMMR_CPTS_CLKSEL register. The recommended RCLK frequency is greater than or equal to VBUS clock frequency. | |
MAIN_PLL0_HSDIV6_CLKOUT | MAIN_PLL0 | |||
CP_GEMAC_CPTS_RFT_CLK | Pin | |||
CPTS0_RFT_CLK | Pin | |||
MCU_EXT_REFCLK0 | Pin | |||
EXT_REFCLK1 | Pin | |||
SERDES0_IP1_LN0_TXMCLK(1) | SERDES0 | |||
MAIN_SYSCLK0 | PLLCTRL0 | |||
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
CPTS0 | CPTS0_RST | MODSS_RST | LPSC0 | CPTS0 hardware reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
CPTS0 | CPTS0_EVNT_PEND_INTR | GICSS0_SPI_IN_129 | GICSS0 | Event pending interrupt | Level |
R5FSS0_CORE0_INTR_IN_129 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_129 | R5FSS0_CORE1 | ||||
R5FSS1_CORE0_INTR_IN_129 | R5FSS1_CORE0 | ||||
R5FSS1_CORE1_INTR_IN_129 | R5FSS1_CORE1 | ||||
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
CPTS0 | - | - | - | No PDMA channels to external DMA engines | - |
Time Sync Event Inputs | |||||
Module Instance | Module Sync Input | Sync Source Signal | Source | Description | Type |
CPTS0 | CPTS0_HW1_PUSH | TIMESYNC_INTRTR0_OUTL_16 | TIMESYNC_INTRTR0 | Asynchronous hardware timestamp 1 push input | Level |
CPTS0_HW2_PUSH | TIMESYNC_INTRTR0_OUTL_17 | TIMESYNC_INTRTR0 | Asynchronous hardware timestamp 2 push input | Level | |
CPTS0_HW3_PUSH | TIMESYNC_INTRTR0_OUTL_18 | TIMESYNC_INTRTR0 | Asynchronous hardware timestamp 3 push input | Level | |
CPTS0_HW4_PUSH | TIMESYNC_INTRTR0_OUTL_19 | TIMESYNC_INTRTR0 | Asynchronous hardware timestamp 4 push input | Level | |
CPTS0_HW5_PUSH | TIMESYNC_INTRTR0_OUTL_20 | TIMESYNC_INTRTR0 | Asynchronous hardware timestamp 5 push input | Level | |
CPTS0_HW6_PUSH | TIMESYNC_INTRTR0_OUTL_21 | TIMESYNC_INTRTR0 | Asynchronous hardware timestamp 6 push input | Level | |
CPTS0_HW7_PUSH | TIMESYNC_INTRTR0_OUTL_22 | TIMESYNC_INTRTR0 | Asynchronous hardware timestamp 7 push input | Level | |
CPTS0_HW8_PUSH | TIMESYNC_INTRTR0_OUTL_23 | TIMESYNC_INTRTR0 | Asynchronous hardware timestamp 8 push input | Level | |
Time Sync Event Outputs | |||||
Module Instance | Module Sync Output | Destination Sync Input | Destination | Description | Type |
CPTS0 | CPTS0_CPTS_GENF0_0 | TIMESYNC_INTRTR0_IN_16 | TIMESYNC_INTRTR0 | Generation Function Output 0 | Edge |
EON_TICK_EVT | TIMER_MGR0 | ||||
CPTS0_CPTS_GENF1_0 | TIMESYNC_INTRTR0_IN_17 | TIMESYNC_INTRTR0 | Generation Function Output 1 | Edge | |
TIMERCLK[0:15] MUX | |||||
CPTS0_CPTS_GENF2_0 | TIMESYNC_INTRTR0_IN_18 | TIMESYNC_INTRTR0 | Generation Function Output 2 | Edge | |
TIMERCLK[0:15] MUX | |||||
CPTS0_CPTS_GENF3_0 | TIMESYNC_INTRTR0_IN_19 | TIMESYNC_INTRTR0 | Generation Function Output 3 | Edge | |
TIMERCLK[0:15] MUX | |||||
CPTS0_CPTS_GENF4_0 | TIMESYNC_INTRTR0_IN_20 | TIMESYNC_INTRTR0 | Generation Function Output 4 | Edge | |
TIMERCLK[0:15] MUX | |||||
CPTS0_CPTS_GENF5_0 | TIMESYNC_INTRTR0_IN_24 | TIMESYNC_INTRTR0 | Generation Function Output 5 | Edge | |
CPTS0_CPTS_SYNC_0 | TIMESYNC_INTRTR0_IN_35 | TIMESYNC_INTRTR0 | Sync Output | Edge | |
CPTS0_CPTS_SYNC_0 | Pin | ||||
Compare Event Outputs | |||||
Module Instance | Module Comp Output | Destination Comp Input | Destination | Description | Type |
CPTS0 | CPTS0_CPTS_COMP_0 | CMPEVT_INTRTR0_IN_82 | CMPEVT_INTRTR0 | Comparison Output | Edge |
CPTS0_CPTS_COMP_0 | Pin |
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset, and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the time sync and compare events routers, see Section 10.3, Time Sync and Compare Events.